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HIGH-VOLTAGE MIXED-SIGNAL IC
128 x 128RGB C-STN LCD Controller-Driver w/ 16-bit per RGB On-Chip SRAM
ES Specifications Revision 0.6
February 7, 2007
ULTRACHIP
The Coolest LCD Drive, Ever!!
Specifications and information herein are subject to change without notice.
UC1697V
128x128RGB CSTN Controller-Driver
TABLE OF CONTENT
INTRODUCTION............................................................................................................... 1 ORDERING INFORMATION ............................................................................................ 2 BLOCK DIAGRAM ........................................................................................................... 3 PIN DESCRIPTION........................................................................................................... 4 RECOMMENDED COG LAYOUT .................................................................................... 8 CONTROL REGISTERS................................................................................................... 9 COMMAND TABLE ........................................................................................................ 12 COMMAND DESCRIPTION ........................................................................................... 14 LCD VOLTAGE SETTING.............................................................................................. 30 VLCD QUICK REFERENCE ............................................................................................. 31 LCD DISPLAY CONTROLS ........................................................................................... 33 ITO LAYOUT AND LC SELECTION .............................................................................. 35 HOST INTERFACE......................................................................................................... 37 DISPLAY DATA RAM .................................................................................................... 44 RESET & POWER MANAGEMENT............................................................................... 47 MULTI-TIME PROGRAM NV MEMORY ........................................................................ 49 MTP OPERATION FOR LCM MAKERS ........................................................................ 50 ESD CONSIDERATION.................................................................................................. 55 ABSOLUTE MAXIMUM RATINGS................................................................................. 56 SPECIFICATIONS .......................................................................................................... 57 AC CHARACTERISTICS................................................................................................ 58 PHYSICAL DIMENSIONS .............................................................................................. 65 ALIGNMENT MARK INFORMATION............................................................................. 66 PAD COORDINATES ..................................................................................................... 67 TRAY INFORMATION .................................................................................................... 72 REVISION HISTORY ...................................................................................................... 73
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UC1697V
128x128RGB CSTN Controller-Driver
UC1697V
Single-Chip, Ultra-Low Power 128COM x 128RGB Matrix Passive Color LCD Controller-Driver INTRODUCTION
UC1697V is an advanced high-voltage mixedsignal CMOS IC, specially designed for the display needs of low power hand-held devices. In addition to low power COM and SEG drivers, UC1697V contains all necessary circuits for highV LCD power supply, bias voltage generation, temperature compensation, timing generation, and graphics data memory. UC1697V employs UltraChip's unique DCC (Direct Capacitor Coupling) driver architecture and LRM (Line Rate Modulation) gray-shade modulation scheme to achieve well balanced shading, vivid colors, and natural-looking images. With UC1697V, LCD makers can now achieve TFT-like image quality, while maintaining the same STN advantages in power consumption, unit cost, ease of customization and production flexibility. * * Support both row-ordered and columnordered display buffer RAM access. Support industry standard 4-wire, 3/4-wire, and 3-wire serial bus (S8, S8uc, S9) and 16-bit/8-bit parallel bus (8080 or 6800). Special driver structure and gray shade modulation scheme. Low power consumption under all display patterns. Fully programmable Mux Rate, partial display window, Bias Ratio and Line Rate allow many flexible power management options. Four software programmable temperature compensation coefficients. Software programmable, self-configuring 10x charge pump. Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements. Pad layouts support COG applications. VDD (digital) range: 1.8V(Typ.) ~ 3.3V VDD (analog) range: 2.6V(Typ.) ~ 3.3V 6.4V ~ 16.5V LCD VOP range: Available MTP trimming supports precise LCD contrast matching. Available in gold bump dies. COM/SEG bump information Bump pitch: 26.5 M Bump gap: 12.0 M 2 Bump surface: 2001 M
*
*
* * *
MAIN APPLICATIONS
* Cellular Phones and other battery operated hand held devices or portable Instruments
* *
FEATURE HIGHLIGHTS
* Single chip controller-driver for 128x128 matrix C-STN LCD with comprehensive support for input format and color depth: 8-bit RGB: 256-color 12-bit RGB: 4K-color 16-bit RGB: 64K-color A software-readable ID bit (ID0) to support configurable vender identification. ID pin (ID1)-switched input data sets (D[7:0] or D[14,12,10,8,6,4,2,0]) for 8-bit mode. Partial scroll function and programmable data update window to support flexible manipulation of screen data.
* *
* * *
Revision A_0.6
1
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
ORDERING INFORMATION
GOLD BUMPED DIE Part Number UC1697VGAA MTP Yes I2 C No Description Gold bumped die, with MTP function.
General Notes
APPLICATION INFORMATION For improved readability, the specification contains many application data points. When application information is given, it is advisory and does not form part of the specification for the device. BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing. There is no post waffle saw/pack testing performed on individual die. Although the latest processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the customer to test and qualify their applications in which the die is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. MTP LIGHT & ESD SENSITIVITY The MTP memory cell is sensitive to photon excitation and ESD. Under extended exposure to strong ambient light, or when TST4 pin is exposed to ESD strikes, the MTP cells can lose its content before the specified memory retention time span. The system designer is advised to provide proper light & ESD shields to realize full MTP content retention performance. LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk. CONTENT DISCLAIMER UltraChip believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. The information and data provided herein is for reference only. No responsibility is assumed by UltraChip for the use of information contained in this datasheet. Always contact UltraChip for commit to mass production for the latest product information and operation parameters. CONTACT INFORMATION UltraChip Inc. (Headquarter) 2F, No. 70, Chowtze Street, Nei Hu District, Taipei 114, Taiwan, R. O. C. Tel: +886 (2) 8797-8947 Fax: +886 (2) 8797-8910 Sales e-mail: sales@ultrachip.com Web site: http://www.ultrachip.com
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
BLOCK DIAGRAM
COLUMN ADDRESS GENERATOR PAGE ADDRESS GENERATOR ROW ADDRESS GENERATOR POWER ON & RESET CONTROL CLOCK & TIMING GENERATOR CONTROL & STATUS REGISTER
DATA RAM I/O BUFFER
LEVEL SHIFTER
DISPLAY DATA RAM
DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS SEG DRIVERS VLCD & BIAS GENERATOR CL
CB0
CB1
COM DRIVERS
Revision A_0.6
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
PIN DESCRIPTION
Name Type # of Pads MAIN POWER SUPPLY VDD2/VDD3 is the analog power supply and it should be connected to the same power source. VDD is the digital power supply and it should be connected to a voltage source that is no higher than VDD2/VDD3. Please maintain the following relationship: VDD2/3 VDD VDD+1.3V Minimize the trace resistance for VDD and VDD2/VDD3. VSS VSS2 GND 12 12 Ground. Connect VSS and VSS2 to the shared GND pin. Minimize the trace resistance for this node. LCD POWER SUPPLY & VOLTAGE CONTROL LCD SEG driving voltages. These are the voltage sources to provide SEG driving currents. These voltages are generated internally. Connect a capacitor, CBX, between VBX+ and VBX- . The resistance of these traces directly affects the driving strength of SEG electrodes and impacts the image of the LCD module. Minimize the trace resistance is critical in achieving high quality image. High voltage LCD Power Supply. When internal VLCD is used, connect these pins together. When external VLCD is used, connect external VLCD source to VLCDIN pins and leave VLCDOUT open. Capacitor CL should be connected between VLCD and VSS. In COG applications, keep the ITO trace resistance under 30 . Description
VDD VDD2 VDD3
PWR
9 9 2
VB1+ , VB1- VB0+ , VB0-
PWR
6, 6 6, 6
VLCD-IN VLCD-OUT
PWR
2 2
NOTE * Recommended capacitor values: CBx : 2.2F/5V or 300x LCD load capacitance, whichever is higher. CL : 330nF (25V) is appropriate for most applications.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
Name
Type
# of Pads HOST INTERFACE
Description Bus mode: The interface bus mode is determined by BM[1:0] and {DB15, DB13} by the following relationship: BM[1:0] 11 10 01 00 01 00 00 {DB15, DB13} Data Data 0x 0x 10 10 11 Mode 6800/16-bit 8080/16-bit 6800/8-bit 8080/8-bit 3-wire SPI w/ 9-bit token (S9: conventional) 4-wire SPI w/ 8-bit token (S8: conventional) 3/4-wire SPI w/ 8-bit token (S8uc: Ultra-Compact)
BM0 BM1
I
1 1
CS0 CS1
I
1 1
Chip Select. Chip is selected when CS1="H" and CS0 = "L". When the chip is not selected, D[15:0] will be high impedance. When RST="L", all control registers are re-initialized by their default states. An RC Filter has been included on-chip. There is no need for external RC noise filter. When RST is not used, connect the pin to VDD. Select Control data or Display data for read/write operation. In S9, CD pin is not used. Connect CD to VSS when not used. "L": Control data "H": Display data Used for production control.
RST
I
1
CD
I
1
ID0
I
1
Connect ID0 to VDD for "H" or VSS for "L". The wiring status of ID0 is available with PID[1:0] of the Get Status command. Select input data set for 8-bit mode. ID1=0 : 8-bit input data are D[0, 2, 4, 6, 8, 10, 12, 14] ID1=1 : 8-bit input data are D[0:7] The wiring status of ID1 is available with PID[1:0] of the Get Status command. Other than 8-bit mode, connect ID1 to VDD for "H" or VSS for "L". WR[1:0] controls the read/write operation of the host interface. See section Host Interface for more detail. In parallel mode, the meaning of WR[1:0] depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used, connect them to VSS.
ID1
I
1
WR0 WR1
I
1 1
Revision A_0.6
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
Name
Type
# of Pads DATA BUS
Description Bi-directional bus for parallel host interfaces. In serial modes, connect DB[0] to SCK, DB[8] to SDA. BM=0x BM=0x BM=01 (8-bit) (8-bit) (S9) ID1=0 ID1=1 D0/D8 D0/D8 DB0 D0 SCK - DB1 D1 D1/D9 - D1/D9 DB2 D2 D2/D10 - - DB3 D3 D3/D11 - D2/D10 DB4 D4 D4/D12 - - DB5 D5 D5/D13 - D3/D11 DB6 D6 D6/D14 - - DB7 D7 D7/D15 - D4/D12 - DB8 D8 SDA - DB9 D9 - - D5/D13 DB10 D10 - - - DB11 D11 - - D6/D14 DB12 D12 - - - - DB13 D13 0 D7/D15 DB14 D14 - - 0 0 DB15 D15 1 Always connect unused pins to either VSS or VDD. BM=1x (16-bit) BM=00 (S8/S8uc) SCK - - - - - - - SDA - - - - 0:S8 / 1:S8uc - 1
D0~D15
I/O
16
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
Name SEG1 ~ SEG384 COM1 ~ COM128
Type
# of Pads
Description HIGH VOLTAGE LCD DRIVER OUTPUT SEG (column) driver outputs. Support up to 128xRGB pixels. Leave unused SEG drivers open-circuit. COM (row) driver outputs. Support up to 128 rows. When designing LCM, always start from COM1. If the LCM has N pixel rows and N is less than 128, set CEN to be N-1, and leave COM drivers [N+1 ~ 128] open-circuit. MISC. PINS Auxiliary VDD. These pins are connected to the main VDD bus within the IC. These pads are provided to facilitate chip configurations in COG application. These pins should NOT be used to provide VDD power to the chip. It is not necessary to connect VDDX to main VDD externally. Test control. This pin has on-chip pull-up resistor. Leave it open during normal operation.
HV
384
HV
128
VDDX
O
5
TST4
I/HV
2
TST4 is also used as one of the high voltage power supply for MTP programming operation. For COG designs, please wire out TST4 with trace resistance between 30~50 . Test I/O pins. Leave these pins open during normal use.
TST1 TST2 NOTE:
O
1 1
Several control registers will specify "0 based index" for COM and SEG electrodes. In those situations, COMX or SEGX will correspond to index X-1, and the value ranges for those index registers will be 0~127 for COM and 0~383 for SEG.
Revision A_0.6
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
RECOMMENDED COG LAYOUT
D15 D14
Dummy COM<20> COM<22> COM<24> COM<26> COM<28> COM<30> COM<32> COM<34> COM<36> COM<38> COM<40> COM<42> COM<44> COM<46> COM<48> COM<50> COM<52> COM<54> COM<56> COM<58> COM<60> COM<62> COM<64> COM<66> COM<68> COM<70> COM<72> COM<74> COM<76> COM<78> COM<80> COM<82> COM<84> COM<86> COM<88> COM<90> COM<92> COM<94> COM<96> COM<98> COM<100> COM<102> COM<104> Dummy
D13 D12 D11 D10 D9
D15 COM<106> COM<108> COM<110> COM<112> COM<114> COM<116> COM<118> COM<120> COM<122> COM<124> COM<126> COM<128>
D8 D7
VDDX D14
D13
D6 D5 D4
D12
D11 D10
D9
D3 D2 D1 D0 RST
D8
D7 D6
D5 D4
D3
WR0 WR1 CD CS0 BM0 BM1 TST4 ID0 ID1
D2
D1 D0
RST WR0 VDDX WR1 CD CS0 VDDX CS1 BM0 VDDX BM1 TST4 TST4
TST1 TST2
ID0 VDDX ID1 VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS Dummy VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VDD VDD VDD VDD VDD VDD VDD
Dummy Dummy Dummy Dummy Dummy Dummy
VDD
Dummy Dummy
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Dummy
VDD3 VDD3 VBO+ VBO+
VB0+
VBO+ VBO+
VB1+ VB1+
VB1+
VB1+ VB1+
VB1VB1-
VB1-
VB1VB1-
VB0VB0-
VB0-
VB0VB0-
VLCd
VLCDIN VLCDIN VLCDOUT VLCDOUT
COM<127> COM<125> COM<123> COM<121> COM<119> COM<117> COM<115> COM<113> COM<111> COM<109> COM<107> COM<105>
COM<18> COM<16> COM<14> COM<12> COM<10> COM<8> COM<6> COM<4> COM<2> SEG<384> SEG<383> SEG<382> SEG<381> SEG<380> SEG<379> SEG<378> SEG<377> SEG<376> SEG<375> SEG<374> SEG<373> SEG<372> SEG<371> SEG<370> SEG<369> SEG<368> SEG<367> SEG<366> SEG<365> SEG<364> SEG<363> SEG<362> SEG<361> SEG<360> SEG<359> SEG<358> SEG<357> SEG<356> SEG<355> SEG<354> SEG<353> SEG<352> SEG<351> SEG<350> SEG<349> SEG<348> SEG<347> SEG<346> SEG<345> SEG<344> SEG<343> SEG<342> SEG<341> SEG<340> SEG<339> SEG<338> SEG<337> SEG<336> SEG<335> SEG<334> SEG<333> SEG<332> SEG<331> SEG<330> SEG<329> SEG<328> SEG<327> SEG<326> SEG<325> SEG<324> SEG<323> SEG<322> SEG<321> SEG<320> SEG<319> SEG<318> SEG<317> SEG<316> SEG<315> SEG<314> SEG<313> SEG<312> SEG<311> SEG<310> SEG<309> SEG<308> SEG<307> SEG<306> SEG<305> SEG<304> SEG<303> SEG<302> SEG<301> SEG<300> SEG<299> SEG<298> SEG<297> SEG<296> SEG<295> SEG<294> SEG<293> SEG<292> SEG<291> SEG<290> SEG<289> SEG<288> SEG<287> SEG<286> SEG<285> SEG<284> SEG<283> SEG<282> SEG<281> SEG<280> SEG<279> SEG<278> SEG<277> SEG<276> SEG<275> SEG<274> SEG<273> SEG<272> SEG<271> SEG<270> SEG<269> SEG<268> SEG<267> SEG<266> SEG<265> SEG<264> SEG<263> SEG<262> SEG<261> SEG<260> SEG<259> SEG<258> SEG<257> SEG<256> SEG<255> SEG<254> SEG<253> SEG<252> SEG<251> SEG<250> SEG<249> SEG<248> SEG<247> SEG<246> SEG<245> SEG<244> SEG<243> SEG<242> SEG<241> SEG<240> SEG<239> SEG<238> SEG<237> SEG<236> SEG<235> SEG<234> SEG<233> SEG<232> SEG<231> SEG<230> SEG<229> SEG<228> SEG<227> SEG<226> SEG<225> SEG<224> SEG<223> SEG<222> SEG<221> SEG<220> SEG<219> SEG<218> SEG<217> SEG<216> SEG<215> SEG<214> SEG<213> SEG<212> SEG<211> SEG<210> SEG<209> SEG<208> SEG<207> SEG<206> SEG<205> SEG<204> SEG<203> SEG<202> SEG<201> SEG<200> SEG<199> SEG<198> SEG<197> SEG<196> SEG<195> SEG<194> SEG<193> SEG<192> SEG<191> SEG<190> SEG<189> SEG<188> SEG<187> SEG<186> SEG<185> SEG<184> SEG<183> SEG<182> SEG<181> SEG<180> SEG<179> SEG<178> SEG<177> SEG<176> SEG<175> SEG<174> SEG<173> SEG<172> SEG<171> SEG<170> SEG<169> SEG<168> SEG<167> SEG<166> SEG<165> SEG<164> SEG<163> SEG<162> SEG<161> SEG<160> SEG<159> SEG<158> SEG<157> SEG<156> SEG<155> SEG<154> SEG<153> SEG<152> SEG<151> SEG<150> SEG<149> SEG<148> SEG<147> SEG<146> SEG<145> SEG<144> SEG<143> SEG<142> SEG<141> SEG<140> SEG<139> SEG<138> SEG<137> SEG<136> SEG<135> SEG<134> SEG<133> SEG<132> SEG<131> SEG<130> SEG<129> SEG<128> SEG<127> SEG<126> SEG<125> SEG<124> SEG<123> SEG<122> SEG<121> SEG<120> SEG<119> SEG<118> SEG<117> SEG<116> SEG<115> SEG<114> SEG<113> SEG<112> SEG<111> SEG<110> SEG<109> SEG<108> SEG<107> SEG<106> SEG<105> SEG<104> SEG<103> SEG<102> SEG<101> SEG<100> SEG<99> SEG<98> SEG<97> SEG<96> SEG<95> SEG<94> SEG<93> SEG<92> SEG<91> SEG<90> SEG<89> SEG<88> SEG<87> SEG<86> SEG<85> SEG<84> SEG<83> SEG<82> SEG<81> SEG<80> SEG<79> SEG<78> SEG<77> SEG<76> SEG<75> SEG<74> SEG<73> SEG<72> SEG<71> SEG<70> SEG<69> SEG<68> SEG<67> SEG<66> SEG<65> SEG<64> SEG<63> SEG<62> SEG<61> SEG<60> SEG<59> SEG<58> SEG<57> SEG<56> SEG<55> SEG<54> SEG<53> SEG<52> SEG<51> SEG<50> SEG<49> SEG<48> SEG<47> SEG<46> SEG<45> SEG<44> SEG<43> SEG<42> SEG<41> SEG<40> SEG<39> SEG<38> SEG<37> SEG<36> SEG<35> SEG<34> SEG<33> SEG<32> SEG<31> SEG<30> SEG<29> SEG<28> SEG<27> SEG<26> SEG<25> SEG<24> SEG<23> SEG<22> SEG<21> SEG<20> SEG<19> SEG<18> SEG<17> SEG<16> SEG<15> SEG<14> SEG<13> SEG<12> SEG<11> SEG<10> SEG<9> SEG<8> SEG<7> SEG<6> SEG<5> SEG<4> SEG<3> SEG<2> SEG<1> COM<1> COM<3> COM<5> COM<7> COM<9> COM<11> COM<13> COM<15> COM<17>
UC1697V Bump View
Dummy COM<19> COM<21> COM<23> COM<25> COM<27> COM<29> COM<31> COM<33> COM<35> COM<37> COM<39> COM<41> COM<43> COM<45> COM<47> COM<49> COM<51> COM<53> COM<55> COM<57> COM<59> COM<61> COM<63> COM<65> COM<67> COM<69> COM<71> COM<73> COM<75> COM<77> COM<79> COM<81> COM<83> COM<85> COM<87> COM<89> COM<91> COM<93> COM<95> COM<97> COM<99> COM<101> COM<103> Dummy
Note for VDD and VSS with COG: The operation condition VDD=1.8V (typical) must be satisfied under all operating conditions. With its high speed data-write condition, UC1697V's peak current (IDD) can be up to ~15mA range during high speed data write to UC1697V's on-chip SRAM. Such high pulsing current mandates very careful design of VDD, VSS ITO trances in COG glass modules. When VDD and VSS trace resistance is not low enough, the pulsing IDD current can cause the actual on-chip VDD to drop below 1.65V and cause the IC to malfunction.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
CONTROL REGISTERS
UC1697V contains registers which control the chip operation. The following table is a summary of these control registers, a brief description and the default values. These registers can be modified by commands, which will be described in the next two sections, starting with a summary table, followed by a detailed instruction-by-instruction description. Name: Default: Name SL The Symbolic reference of the register. Note that, some symbol name refers to bits (flags) within another register. Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset. Bits 7 Default 0H Description Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is between 0 (no scrolling) and (127 - 2x(FLT+FLB)). Setting SL outside of this range causes undefined effect on the displayed image. Fixed Lines. The top FLTx2 and bottom FLBx2 lines (relative to CEN) of each frame are fixed and are not affected by scrolling (SL). When FLT and/or FLB are non-zero, the screen is effectively separated into three regions: one scrollable, surrounded by two non-scrollable regions. When partial display mode is activated, the display of these 2xFLT and 2xFLB lines is also controlled by LC[0]. When LC[0]=1, the display will have three sections: 2xFLT on one side non-scrollable, 2xFLB on the other side also non-scrollable, and scrollable DST~DEN in the middle. CA RA BR 7 7 3 0H 0H 3H Display Data RAM Column Address (counted in RGB triplet) (Used in Host to Display Data RAM access) Display Data RAM Row Address (Used in Host to Display Data RAM access) Bias Ratio. The ratio between VLCD and VBIAS. 000b : 6 001b : 10 010b : 11 100b : 9 Temperature Compensation (per oC) 00b : -0.00% 01b : -0.10% 10b : -0.15% 11b : -0.05% Electronic Potentiometer to fine tune VBIAS and VLCD PM offset. PMO[5]=1: The effective PM value, PMV = PM - PMO[4:0] PMO[5]=0: The effective PM value, PMV = PM + PMO[4:0] PC 4 EH Power Control. PC[1:0] : 0xb: LCD: 13nF PC[3:2] : 00b: External VLCD Address Control: AC[0] : WA: Automatic column/row Wrap Around (1 : ON) AC[1] : Auto-Increment order 0 : Column (CA) first 1 : Row (RA) first AC[2] : RID: RA (row address) auto increment direction (0 : +1 1 : -1) AC[3] : Window Program Mode 0 : Inside Mode: Write to SRAM within the window defined by (WPC0, WPP0), (WPC1, WPP1) 1 : Outside Mode: Write to SRAM but skip the window defined by (WPC0, WPP0), (WPC1, WPP1) 1xb: 13 < LCD < 22nF 11b: Internal VLCD (10x charge pump) 011b : 12
FLT FLB
4 4
0H 0H
TC
2
0H
PM PMO
8 6
5CH 00H
AC
4
1H
Revision A_0.6
9
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
Name DC
Bits 5
Default 18H
Description Display Control: DC[0] : PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF) DC[1] : APO: All Pixels ON (Default 0: OFF) DC[2] : Display ON/OFF (Default 0: OFF) When DC[2] is set to 0, the IC will enter Sleep mode. DC[3] : Gray-shade Modulation mode. 0 : On/Off mode 1 : 32-shade Mode DC[4] : Green Enhance Mode. Only valid in 4K-color mode. 0 : Enable. Allows an extra display bit for green color. 1 : Disable LCD Control: LC[0] : Enable the top FLTx2 and bottom FLBx2 lines in partial display mode (Default OFF). LC[1] : MX, Mirror X. SEG/Column sequence inversion (Default: OFF) LC[2] : MY, Mirror Y. COM/Row sequence inversion (Default: OFF) LC[4:3] : Line Rate (Klps: Kilo-Line-per-second) 00b : 20.1 Klps 01b : 24.4 Klps 10b : 29.6 Klps 11b : 35.8 Klps Line Rate (for 8-color On/Off mode) 00b : 5.5 Klps 01b : 6.6 Klps 10b : 8.0 Klps 11b : 9.7 Klps (Line-Rate = Frame-Rate x Mux-Rate) LC[5] : RGB filter order (as mapped to SEG1, SEG2, SEG3) 0 : BGR-BGR 1 : RGB-RGB LC[7:6] : Color and input mode when DC[4]=1: 00b : 256 color mode 3R-3G-2B ( 8-bit/RGB) 01b : 4K color mode 4R-4G-4B (12-bit/RGB) 10b : 64K color mode 5R-6G-5B (16-bit/RGB) when DC[4]=0: 00b : 256 color mode 3R-3G-2B ( 8-bit/RGB) 01b : 4K color mode 4R-5G-3B (12-bit/RGB) 10b : 64K color mode 5R-6G-5B (16-bit/RGB) LC[9:8] : Partial Display Control 0xb: Disable Mux-Rate = CEN+1 (DST, DEN not used) 10b: Enabled Mux-Rate = CEN+1 11b: Enabled Mux-Rate = DEN-DST+1+LC[0] x (FLT+FLB) x 2 N-Line Inversion: NIV[5:0] : 00000b: Disable 00001b ~ 111111b: 1~ 63 lines ( Default: 17lines ) NIV[6] : 0b: no-XOR 1b: XOR
LC
10
090H
NIV
7
51H
CSF
3
0H
COM Scan Function CSF[0] : 0b : LRM sequence: AEBCD-AEBCD 1b : LRM sequence: AEBCD-EBCDA CSF[1] : 0b :FRC Disable 1b : FRC Enable CSF[2] : Shade-1 / Shade-30 option 0 : Dither directly on input data (SRAM Change) 1 : PWM on SEG output stage
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
Name CEN DST DEN
Bits 7 7 7
Default 7FH 00H 7FH
Description COM scanning end (last COM with full line cycle, 0 based index) Display start (first COM with active scan pulse, 0 based index) Display end (last COM with active scan pulse, 0 based index) Please maintain the following relationship: CEN = the actual number of pixel rows on the LCD - 1 CEN DEN DST+ 9
WPC0 WPP0 WPC1 WPP1 MTPC
7 7 7 7 5
00H 00H 7FH 7FH 10H
Window program starting column address. Value range: 0 ~127. Window program starting row address. Value range: 0~127. Window program ending column address. Value range: 0~127. Window program ending row address. Value range: 0~127. MTP Programming Control: MTPC[2:0] : MTP command 000 : Idle 001 : Read 010 : Erase 011 : Program 1xx : For UltraChip's debug use only MTPC[3] : MTP Enable (automatically cleared after each MTP command) MTPC[4] : Ignore/Use MTP. 0: Ignore 1: Use
MTP MTPM APC OM
6 6 2 2
-00H N/A -
Multiple-Time Programming. For VLCD fine tune. MTP Write Mask. Bit =1: program, Bit=0: no action. Advanced Program Control. For UltraChip only. Please do not use. Status Registers Operating Modes (Read only) 00b: Reset 01b: (Not used) 10b: Sleep 11b: Normal MTP option flag: 1 for MTP version, 0 for non-MTP version. MTP programming in-progress MTP Operation Succeeded Access the connected status of ID pins.
MD MS WS ID
1 1 1 2
- - - PIN
Revision A_0.6
11
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
COMMAND TABLE
The following is a list of host commands supported by UC1697V C/D: 0: Control, 1: Data W/R: 0: Write Cycle, 1: Read Cycle #: Useful Data bits -: Don't Care
Command 1 Write Data Byte 2 Read Data Byte 3 Get Status & PM 4 5 6 7 8 9 10 11 12 13 Set Column Address LSB Set Column Address MSB Set Temp. Compensation Set Panel Loading Set Pump Control Set Adv. Program Control (double-byte command) Set Scroll Line LSB Set Scroll Line MSB Set Row Address LSB Set Row Address MSB Set VBIAS Potentiometer (double-byte command) Set Partial Display Control Set RAM Address Control C/D W/R 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 # # GE Ver 0 0 0 0 0 0 # 0 0 0 0 1 # 1 1 1 # 1 1 1 1 1 1 1 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 1 1 D4 D3 D2 # # # # # # WA DE WS PMO[6:0] Product Code PID[2:0] 0 0 0 # # 0 0 1 0 # 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 # # # # # 1 0 0 # # 1 0 1 0 # 1 1 0 # # 1 1 1 0 # 0 0 0 0 0 # # # # # 0 0 0 0 1 0 0 0 1 # 0 0 1 0 0 # # # # # 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 # 1 0 0 0 # 1 0 0 1 0 # # # # # 1 0 1 0 0 1 0 1 0 1 1 0 1 1 # 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 # # # # # 1 1 0 1 # 1 1 1 0 0 # # # # # 1 1 1 0 0 # # # # # 1 1 1 0 0 # # # # # 1 1 1 0 1 # # # # # 1 1 1 0 1 # # # # # 1 1 1 0 1 # # # # # 1 1 1 0 1 # # # # # 1 1 1 1 0 0 1 1 1 0 # # # 0 1 1 1 0 # # # # D6 # # MX D5 # # MY D1 # # MD 0 # # # # # R # # # # # 0 # # # 0 # # 0 1 # # 0 # 0 # # 1 1 TT # # 0 # 1 # 1 # 0 # 0 # 1 # 1 # 0 0 # 0 # # # 1 # 0 # 1 # 0 # 1 # 0 # 1 # # 0 # 1 # D0 # # MS 0 # # # # # R # # # # # 1 # # # 0 # # # # # # 0 # # # # 0 1 Action Default Write 1 byte N/A Read 1 byte N/A Get {Status, Ver, N/A PMO, Product Code, Product Code PID, MID} (5h) Set CA[3:0] 0 Set CA[6:4] 0 Set TC[1:0] 00b Set PC[1:0] 1xb Set PC[3:2] 11b Set APC[R][7:0], N/A R = 0, 1, or 2 Set SL[3:0] 0 Set SL[6:4] 0 Set RA[3:0] 0 Set RA[6:4] 0 Set PM[7:0] Set LC[9:8] Set AC[2:0] Set {FLT, FLB} Set LC[4:3] Set DC[1] Set DC[0] Set DC[4:2] Set LC[2:0] Set NIV[6:0] Set LC[5] Set LC[7:6] Set CSF[2:0] System Reset No operation For testing only. Do not use. Set BR[2:0] Set CEN[6:0] Set DST[6:0] Set DEN[6:0] Set WPC0 Shared Set with WPP0 MTP Set Commands WPC1 Set WPP1 Set AC[3] Set MTPC[4:0] Set MTPM[5:0] 5CH 0xH 001b 0 10b 0b 0b 110b 000b 51H 0 (BGR) 10b 000b N/A N/A N/A 011b: 12 127 0 127 0 0 127 127 0: Inside 10H 0
14 Set Fixed Lines 15 16 17 18 19 Set Line Rate Set All-Pixel-ON Set Inverse Display Set Display Enable Set LCD Mapping Control
20 Set N-Line Inversion 21 22 23 24 25 Set Color Pattern Set Color Mode Set COM Scan Function System Reset NOP Set Test Control 26 (double-byte command) 27 Set LCD Bias Ratio 28 Set COM End 29 Set Partial Display Start 30 Set Partial Display End 31 32 33 34 35 36 Set Window Program Starting Column Address Set Window Program Starting Row Address Set Window Program Ending Column Address Set Window Program Ending Row Address Window Program Mode Set MTP Operation control
37 Set MTP Write Mask
12
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
Command 38 Set VMTP1 Potentiometer 39 Set VMTP2 Potentiometer 40 Set MTP Write Timer 41 Set MTP Read Timer
C/D W/R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D7 1 # 1 # 1 # 1 #
D6 1 # 1 # 1 # 1 #
D5 1 # 1 # 1 # 1 #
D4 1 # 1 # 1 # 1 #
D3 0 # 0 # 0 # 0 #
D2 1 # 1 # 1 # 1 #
D1 0 # 0 # 1 # 1 #
D0 0 # 1 # 0 # 1 #
Action Set MTP1 Set MTP2 Set MTP3 Set MTP4
Default N/A N/A N/A N/A
Shared with Window Program commands
NOTE: * All bit patterns other than commands listed above, may result in undefined behavior.
* The interpretation of commands (37)~(41) depends on the setting of register MTPC[3]. o Commands (38)~(41) are shared with commands (31)~(34). These two sets of commands share exactly the same code and control registers. When MTPC[3]=0, they are interpreted as Window Program commands and registers. When MTPC[3]=1, they function as MTP Control commands and registers. * After MTP ERASE or PROGRAM operation, before resuming normal operation, please always a) Remove TST4 power source, b) Do a full VDD ON-OFF-ON cycle.
* Under 16-bit bus mode and CD=0, D[15:8] is ignored and only D[7:0] is used. As a result, the bus cycles for commands under 16-bit bus and 8-bit bus are the same, and double-byte commands still need two bus cycles under 16-bit bus mode. Example: 8-bit bus mode: Set PL[1:0] = 2'b11 : Set PM[7:0] = 8'h8b : 1
st nd
D[7:0] = 0010 1011 D[7:0] = 1000 0001 D[7:0] = 1000 1011
2 16-bit bus mode: Set PL[1:0] = 2'b11:
D[15:0] = 0000 0000
0010 1011 1000 0001 1000 1011
Set PM[7:0] = 8'h8b: 1st D[15:0] = 0000 0000 2
nd
D[15:0] = 0000 0000
Revision A_0.6
13
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
COMMAND DESCRIPTION
(1) WRITE DATA TO DISPLAY MEMORY Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Write data 1 0 8-bit data write to SRAM UC1697V will convert input RAM data to 16-bit of RGB data. Please refer to command Set Color Mode for detail of data-write sequence. (2) READ DATA FROM DISPLAY MEMORY Action Read data C/D W/R D7 1 1 D6 D5 D4 D3 D2 D1 D0 8-bit data from SRAM
Each RGB triplet is stored as 16-bit in the display RAM. Each 16-bit of RGB data takes 1 / 2 RAM read cycles for 16 / 8 - bit bus mode, respectively. The read out RGB data is after-extension for 64K color mode.
R4 R3 R2
st
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
1 8-bit Read
2
nd
8-bit Read
Write/Read Data Byte (command (1) / (2)) operation uses internal Row Address register (RA) and Column Address register (CA). RA and CA can be programmed by issuing commands Set Row Address and Set Column Address. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0 or 127), RA will be wrapped around to the other end of RAM and continue. (3) GET STATUS & PM Action Get Status & PM C/D W/R D7 0 0 0 1 1 1 D6 D5 D4 D3 D2 D1 D0 GE MX MY WA DE WS MD MS Ver Product Code PMO[5:0] PID[2:0] 0 0
Status1 definitions: GE: Green Enhancing enable flag. Green Enhance Mode is disabled when GE = 1. MX: Status of register LC[1], mirror X. MY: Status of register LC[2], mirror Y. WA: Status of register AC[0]. Automatic column/row wrap around. DE: Display enable flag. DE=1 when display is enabled WS: MTP Operation succeeded MD: MTP Option (1 for MTP version, 0 for non-MTP version) MS: MTP action status Status2 definitions: Ver: Version Code. 00 ~ 11. PMO[5:0]: PM offset value. Status3 definitions: Product Code: 1110b (Eh) PID[1:0]: Provide access to ID pins connection status. If multiple Get Status commands are issued consecutively within one single CD 1 0 1 transaction, the Get Status command will return {Status1, Status2, Status3, Status1, Status2, Status3, Status1..} alternately.
14
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(4) SET COLUMN ADDRESS Action Set Column Address LSB CA[3:0] C/D W/R D7 0 0 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CA3 CA2 CA1 CA0
0 0 0 1 0 CA6 CA5 CA4 Set Column Address MSB CA[6:4] 0 0 Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG electrode. CA value range: 0~127 (5) SET TEMPERATURE COMPENSATION Action C/D W/R D7 D6 D5 D4 0 D3 0 D2 1 D1 D0 0 0 1 Set Temperature Comp. TC[1:0] 0 0 Set VBIAS temperature compensation coefficient (%-per-degree-C) Temperature compensation curve definition: 00b = -0.00%/oC 01b = -0.10%/oC (6) SET PANEL LOADING Action C/D W/R D7 D6 D5 D4 0 D3 1 D2 0 D1 D0 0 0 1 Set Panel Loading PC[1:0] 0 0 Set PC[1:0] according to the capacitance loading of LCD panel. Panel loading definition: 0xb: LCD: 13nF (7) SET PUMP CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 PC3 PC2 Set Pump Control PC[3:2] 0 0 Set PC[3:2] to program the build-in charge pump stages. Always make sure the IC is in a RESET state before changing PC[3:2] value. Avoid changing PC[3:2] setting when the display is enabled. Pump control definition: 00b = External VLCD 11b = Internal VLCD (x10) 1xb: LCD: 13~22nF PC1 PC0 TC1 TC0
10b = -0.15%/oC
11b = -0.05%/oC
(8) SET ADVANCED PROGRAM CONTROL Action Set APC[R][7:0] (Double-byte command) For UltraChip only. Please do NOT use. C/D W/R D7 0 0 0 0 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 R D0 R
APC register parameter
Revision A_0.6
15
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(9) SET SCROLL LINE Action Set Scroll Line LSB SL[3:0] Set Scroll Line MSB SL[6:4] Set the number of lines for scroll area. C/D W/R D7 0 0 0 0 0 0 D6 1 1 D5 0 0 D4 0 1 D3 0 D2 D1 D0 SL3 SL2 SL1 SL0 SL6 SL5 SL4
Scroll line setting will scroll the displayed image up by SL rows. The valid value for SL is between 0 (no scrolling) and 127-2x(FLT+FLB) (full scrolling). FLT and FLB are the register values programmed by the Set Fixed Lines command. Fixed Area (2xFLT rows) Image row 0 : Scroll Area Image row N-1 Image row N : : Image row 127-2xFL SL=0 row 0 : row 2xFLT-1 row 2xFLT : : Fixed Area (2xFLT rows) Image row N : Scroll Area : Image row 127-2xFL Image row 0 : Image row N-1 SL=N row 0 : row 2xFLT-1 row 2xFLT : :
row 127
row 127
(10) SET ROW ADDRESS Action Set Row Address LSB RA [3:0] C/D W/R D7 0 0 0 0 0 D6 1 1 D5 1 1 D4 0 1 D3 0 D2 D1 D0 RA3 RA2 RA1 RA0 RA6 RA5 RA4
Set Row Address MSB RA [6:4] 0 Set SRAM row address for read/write access. Possible value = 0~127 (11) SET VBIAS POTENTIOMETER Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1 0 0 0 0 0 0 1 Set VBIAS Potentiometer. PM [7:0] 0 0 (Double-byte command) 0 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Program VBIAS Potentiometer (PM[7:0]). See section LCD Voltage Setting for more detail. Effective range: 0 ~ 255
16
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(12) SET PARTIAL DISPLAY CONTROL Action C/D W/R D7 D6 0 D5 0 D4 0 D3 0 D2 1 D1 D0 1 Set Partial Display Enable LC [9:8] 0 0 This command is used to enable partial display function. LC9 LC8
LC[9:8] : 0xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.) 10b: Enable Partial Display, Mux-Rate = CEN+1 11b: Enable Partial Display, Mux-Rate = DEN-DST+1+ LC[0]x(FLT+FLB)x2 (13) SET RAM ADDRESS CONTROL Action Set AC [2:0] C/D W/R D7 0 0 1 D6 0 D5 0 D4 0 D3 1 D2 D1 D0 AC2 AC1 AC0
Program registers AC[2:0] for RAM address control. AC[0]: WA, Automatic column/row wrap around. 0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary 1: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step. AC[1]: Auto-Increment order 0 : column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1). 1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1). AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 ) When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by +1 or -1. AC[2:0] controls the auto-increment behavior of CA and RA. For Window Program enabling (AC[3]=ON), see section Command Description (34) ~ (37) for more details. If WPC[1:0] and WPP[1:0] values are the default values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[3] is.
Revision A_0.6
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(14) SET FIXED LINES Action Set Fixed Lines {FLT, FLB} (Double-byte command) C/D W/R D7 0 0 1 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0
0 0 FLT[3:0] FLB[3:0] The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and fixed area. The Set Fixed Lines command will define the fixed area, which will not be affected by the SL scroll function. The fixed area covers the top 2xFLT and bottom 2xFLB rows for mirror Y (MY) is 0, or covers the top 2xFLB and bottom 2xFLT rows for MY=1. One example of the visual effect on LCD is illustrated in the figure below.
Fixed Area
1
Fixed Area
1
(2xFLT)
Scroll Area
(2xFLB)
Scroll Area
Fixed Area
Fixed Area
(2xFLB) MY = 0
128
(2xFLT) MY = 1
128
When partial display mode is activated, the display of these 2x(FLT+FLB) lines is also controlled by LC[0]. Before turning on LC[0], please make sure MY=0 DST DEN FLTx2 (CEN-FLBx2). MY=1 DST DEN FLBx2 (CEN-FLTx2)
(15) SET LINE RATE Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 0 LC4 LC3 Set Line Rate LC [4:3] 0 0 Program LC [4:3] for line rate setting (Frame-Rate = Line-Rate / Mux-Rate). The line rate is automatically scaled down by 2/3, 1/2, 1/3 and 1/4 at Mux-Rate = 87, 65, 44 and 33. The following are line rates at Mux Rate = 88 ~ 128. 00b: 20.1 Klps 01b: 24.4 Klps In On/Off Mode 00b: 5.5 Klps 01b: 6.6 Klps (Klps: Kilo-Line-per-second) (16) SET ALL PIXEL ON Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 0 DC1 Set All Pixel ON DC [1] 0 0 Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data stored in display RAM. (17) SET INVERSE DISPLAY Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 1 DC0 Set Inverse Display DC [0] 0 0 Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This function has no effect on the existing data stored in display RAM. 10b: 29.6 Klps 10b: 8.0 Klps 11b: 35.8 Klps 11b: 9.7 Klps
18
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(18) SET DISPLAY ENABLE Action C/D W/R D7 1 D6 0 D5 1 D4 0 D3 1 D2 D1 D0 Set Display Enable DC [4:2] 0 0 This command is for programming register DC[4:2]. DC4 DC3 DC2
When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing circuit will be halted to conserve power. When DC[2] is set to 1, UC1697V will first exit from Sleep mode, restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or timing sequence required to enter or exit the Sleep mode. DC[3] controls the gray shade modulation modes. UC1697V has two gray shade modulation modes: an On/Off mode and a 32-shade mode. The modulation curves are shown below. Horizontal axes are the gray shade data. The vertical axes are the ON-OFF ratio.
50 45 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28
DC[4] Green Enhance Mode. Refer to command Set Color Mode for more information. 0b: Green Enhancing Mode enabled NOTE: 1. For red and blue colors, shades mapped to data 1 and 30 (shown as red points above) are achieved by special dithering. This will be solved when the PWM function is enabled. 2. Green shades are created by combining FRC and special dithering. Six of the shades (1, 2, 3, 59, 60, and 61) are created by special dithering. This will be solved when the PWM function is enabled. Data 62 and 63 are mapped to the same shade. 3. When the internal DC-DC converter starts to operate and pump out current to VLCD, there will be an inrush pulse current between VDD2 and VSS2 initially. To avoid this current pulse from causing potential harmful noise, do NOT issue any command or write any data to UC1697V for 5~10mS after setting DC[2] to 1. 1b: Green Enhancing Mode disabled
Revision A_0.6
19
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(19) SET LCD MAPPING CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 MY MX LC0 Set LCD Mapping Control LC [2:0] 0 0 This command is used for programming LC[2:0] to control COM (row) mirror (MY), SEG (column) mirror (MX). LC[2] controls Mirror Y (MY): MY is implemented by reversing the mapping order between RAM and COM electrodes. The data stored in RAM is not affected by the MY action. MY will have immediate effect on the display image. LC[1] controls Mirror X (MX): MX is implemented by selecting the CA or 127-CA as write/read (from host interface) display RAM column address so this function will only take effect after rewriting the RAM data. LC[0] controls whether soft icon sections (2xFLT, 2xFLB) are displayed during partial display mode. (20) SET N-LINE INVERSION Action Set N-line Inversion, NIV[4:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0
NIV6 NIV5 NIV4 NIV3 NIV2 NIV1 NIV0
N-Line Inversion: NIV[5:0]: 000000b: Disable 000001b ~ 111111b: 1~63 lines ( Default : 17 lines ) NIV[6]: 0b: non-XOR 1b: XOR 13 13 13 NIV[6]=1 13 Frame 1 2 13 Frame 2 13 11 13 11 2 13 13 13
NIV[6]=0
(21) SET COLOR PATTERN Action C/D W/R D7 D6 D5 D4 D3 D2 D1 0 D0 LC5 1 1 0 1 0 0 Set Color Pattern LC [5] 0 0 UC1697V supports on-chip swapping of R B data mapping to the SEG drivers.
SEG388 SEG389 SEG390 LC[5] SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 ... 0 B G R B G R ... B G R 1 R G B R G B ... R G B The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Mode below.
20
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(22) SET COLOR MODE Action C/D W/R D7 D6 D5 D4 D3 D2 1 D1 D0 1 1 0 1 0 Set Color Mode LC [7:6] 0 0 Program color mode and RGB input pattern. Color mode (LC[7:6]) definition: Note: For serial bus modes, please refer to 8-bit tables below. Green Enhance Mode disabled (DC[4] = 1): LC[7:6] = 00b ( RRR-GGG-BB, 256-color ) 8 bits of input RGB data are stored to 16 RAM bits. No dither is performed. Data Write Sequence (8-bit) 1st Write Data Cycle Data Write Sequence (16-bit) 1st Write Data Cycle D[7:0] R2 R1 R0 G2 G1 G0 B1 B0 D[15:0] 000 0 0 0 0 0 R2 R1 R0 G2 G1 G0 B1 B0 LC7 LC6
LC[7:6] = 01b ( RRRR-GGGG-BBBB, 4K-color ) 12 bits of input RGB data are stored to 16 RAM bits. No dither is performed. Every 3 bytes of input data will be merged into 2 sets of RGB data. Data Write Sequence (8-bit) 1st Write Data Cycle 2nd Write Data Cycle 3rd Write Data Cycle Data Write Sequence (16-bit) 1st Write Data Cycle 2nd Write Data Cycle D[7:0] R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 D[15:0] 000 000 0 0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 64K-color ) 16 bits of input data are stored to 16 RAM bits directly. Data Write Sequence (8-bit) 1st Write Data Cycle 2nd Write Data Cycle Data Write Sequence (16-bit) 1st Write Data Cycle D[7:0] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 D[15:0] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Revision A_0.6
21
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
Green Enhance Mode enabled (DC[4]=0): LC[7:6] = 00b ( RRR-GGG-BB, 256-color ) 8 bits of input RGB data are stored to 16 RAM bits. No dither is performed. Data Write Sequence (8-bit) 1st Write Data Cycle Data Write Sequence (16-bit) 1st Write Data Cycle D[7:0] R2 R1 R0 G2 G1 G0 B1 B0 D[15:0] 000 0 0 0 0 0 R2 R1 R0 G2 G1 G0 B1 B0
LC[7:6] = 01b ( RRRR-GGGGG-BBB, 4K-color ) 12 bits of input data are extended and stored to 16 RAM bits. Every 3 bytes of input data will be merged into 2 sets of RGB data. Data Write Sequence (8-bit) 1st Write Data Cycle 2nd Write Data Cycle 3rd Write Data Cycle Data Write Sequence (16-bit) 1st Write Data Cycle 2nd Write Data Cycle D[7:0] R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0 R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0 D[15:0] 000 000 0 0 R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0 R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0
LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 64K-color ) The behaviors of 8-bit input mode and 16-bit input mode do not change with DC[4] setting. Refer to previous section for more information on these two input modes. (23) SET COM SCAN FUNCTION Action Set COM Scan Function CSF[2:0] C/D W/R D7 0 0 1 D6 1 D5 0 D4 1 D3 1 D2 D1 D0
CSF2 CSF1 CSF0
COM scan function CSF[0]: LRM sequence option 0b: LRM sequence: AEBCD-AEBCD 1b : LRM sequence: AEBC-EBCDA CSF[1]: FRC option 0b: FRC Disable 1b: FRC Enable CSF[2]: Shade-1, Shade-30 option 0 : Dither directly on input data(SRAM Change) 1 : PWM on SEG output stage (24) SYSTEM RESET Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 1 0 System Reset 0 0 This command will activate the system reset. Control register values will be reset to their default values. Data stored in RAM will not be affected. (25) NOP Action C/D W/R D7 0 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 No Operation 0 This command is used for "no operation".
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(26) SET TEST CONTROL Action Set TT (Double-byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 D0 TT
0 0 Testing parameter This command is used for UltraChip production testing. Do NOT use. (27) SET LCD BIAS RATIO Action Set Bias Ratio BR [2:0] Bias ratio definition: 000b = 6 001b = 10 100b = 9 (28) SET COM END Action Set CEN [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 C/D W/R D7 0 0 1 D6 1 D5 1 D4 0 D3 1 D2 D1 D0 BR2 BR1 BR0
010b = 11
011b = 12
CEN register parameter
This command programs the ending COM electrode. CEN defines the number of used COM electrodes, and it should correspond to the number of pixel-rows in the LCD. When the LCD has less than 128 pixel rows, the LCM designer should set CEN to N-1 (where N is the number of pixel rows) and use COM1 through COM-N as COM driver electrodes. (29) SET PARTIAL DISPLAY START Action Set DST [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 1 D0 0
DST register parameter
This command programs the starting COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse.
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(30) SET PARTIAL DISPLAY END Action Set DEN [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 1 D0 1
DEN register parameter
This command programs the ending COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse. CEN, DST, and DEN are 0-based indexes of COM electrodes. They control only the COM electrode activity, and do not affect the mapping of display RAM to each COM electrodes. The image displayed by each pixel row is therefore not affected by the setting of these three registers. When LC[9]=1, two partial display modes are possible with UC1697V: LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate 33, set BR=6). LC[8]=0: Full gray shade low power mode (BR and PM stays the same) When LC[9:8]=10b, the Mux-Rate is still CEN+1. This is achieved by suppressing only the scanning pulses, but not the scanning time slots, for COM electrodes that is outside of DST~DEN. Under this mode, the grayscale quality of the display is preserved, while the power can be reduced significantly. When LC[9:8]=11b, the Mux-Rate is narrowed down DEN-DST +1 + 2x(FLT+FLB)xLC[0]. When MUX rate is reduced, reduce the line rate accordingly to reduce power. Changing MUX rate also require BR and VLCD to be readjusted. When Mux-Rate is under 33, it is recommend to set BR=6. For minimum power consumption, set LC[9:8]=11b, set (DST, DEN, FL, CEN) to minimize MUX rate, use slowest line rate which satisfies the flicker requirement, use On-Off mode, set PC[1:0]=00b, and use lowest BR, lowest VLCD which satisfies the contrast requirement. In either case, DST/DEN defines a small subsection of the display which will remain active while shutting down all the rest of the display to conserve energy. Scan Method when LC[9:8]=10b 0 .. DST DEN CEN .. 127 Pulse Enable Pulse Disable Not Scanned Pulse Enable Not scanned Not scanned Display segment Pulse Disable Scan Method when LC[9:8]=11b: Not scanned
Display Result:
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(31) SET WINDOW PROGRAM STARTING COLUMN ADDRESS Action Set WPC0 [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0
WPC0 register parameter
This command is to program the starting column address of RAM program window. (32) SET WINDOW PROGRAM STARTING ROW ADDRESS Action Set WPP0 [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1
WPP0 register parameter
This command is to program the starting row address of RAM program window. (33) SET WINDOW PROGRAM ENDING COLUMN ADDRESS Action Set WPC1 [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 0
WPC1 register parameter
This command is to program the ending column address of RAM program window. (34) SET WINDOW PROGRAM ENDING ROW ADDRESS Action Set WPP1 [6:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1
WPP1 register parameter
This command is to program the ending row address of RAM program window.
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(35) SET WINDOW PROGRAM MODE Action Set Window Program Enable AC[3] C/D W/R D7 0 0 1 D6 1 D5 1 D4 1 D3 1 D2 0 D1 0 D0 AC3
This command controls the Window Program function. AC[3]=0: Inside Mode When Window Programming is under "Inside" mode , the CA and RA increment and wrap-around will be performed automatically around the boundaries as defined by registers WPC0, WPC1, WPP0, and WPP1, so that the CA/RA address will stay within the defined window of SRAM address, and therefore allow effective data update within the window. AC[3]=1: Outside Mode When Window Programming is under "Outside" mode, the CA and RA increment and wrap-around boundary will cover the entire UC1697V SRAM map (CA: 0~127, RA:0~127). However, when CA/RA points to a memory location within the window defined by registers WPC0, WPC1, WPP0, and WPP1, the SRAM data update operation will be suspended, the existing data will be retained and the input data will be ignored. The direction of Window Program will depend on the WA (AC[0]), RID (AC[2]), auto-increment order (AC[1]) and MX (LC[1]) register setting. WA decides whether the program RAM address advances to next row/column after reaching the specified window column / row boundary. RID controls the RAM address incrementing from WPP0 toward WPP1 (RID=0) or reverse the direction (RID=1). Auto-increment order directs the RAM address increment vertically (AC[1]=1) or horizontally (AC[1]=0). MX results the RAM column address incrementing from 127-WPC0 to 127-WPC1 (MX=1) or WPC0 to WPC1 (MX=0). By different combination of RID, AC[1], MX, and by setting CA, RA at proper corners of the "window", effects such as mirrors and rotations can be easily achieved. Setting or resetting AC[3] does not affect the values of CA and RA. So, always remember to reposition CA and RA properly after changing the setting of AC[3].
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
Display Data Direction
Function Setting AIO AC[1] MX LC[1] RID AC[2]
Image in the Host (MPU) (Start :
Image in Display Data Ram (Physical origin: upper left corner)
Normal
0
0
0
Y-mirror
0
0
1
X-mirror
0
1
0
X-mirror Y-mirror
0
1
1
X-Y Exchange
1
0
0
X-Y Exchange Y-mirror
1
0
1
X-Y Exchange X-mirror
1
1
0
X-Y Exchange X-mirror Y-mirror
1
1
1
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
(36) SET MTP OPERATION CONTROL Action Set MTPC [4:0] (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0
MTPC register parameter
This command is for MTP operation control: MTPC[2:0] : MTP command 000 : Sleep 010 : MTP Erase 1xx : For UltraChip use only. MTPC[3] : MTPC[4] : 001 : MTP Read 011 : MTP Program
MTP Enable ( automatically cleared each time after MTP command is done ) MTP value valid (ignore MTP value when L )
DC[2] and MTPC[3] are mutually exclusive. Only one of these two control flags can be set to ON at any time. In other words, when DC[2] is ON, all MTP operations will be blocked, and, when MTP operation is active, set DC[2] to 1 will be blocked.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
The following commands, (37) ~ (41), are used as MTP commands only when MTPC[3]=1. (37) SET MTP WRITE MASK Action Set MTPM [6:0] (Triple-byte command) C/D W/R D7 0 0 0 0 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1
MTPM register parameter
This command enables Write to each of the 7 individual MTP bits. When MTPM[x]=1, the x-th bit of the MTP memory will be programmed to "1". MTPM[x]=0 means no Write action for x-th bit. And the content of this bit will not change. The amount of "programming current" increases with the number of 1's in MTPM. If the "programming current" appears to be too high for the LCM design (e.g. TST4 ITO trace is not wide enough to supply the current), use multiple write cycles and distribute the 1's evenly into these cycles. MTPM[6:0] : Set PMO value MTPM1[1:0]: Set MID value This command is only valid when MTPC[3]=1. (38) SET VMTP1 POTENTIOMETER Action Set MTP1 (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0
Shared register parameter
This command is for fine tuning VOPT1 setting (use with BR=000) and is only valid when MTPC[3]=1. (39) SET VMTP2 POTENTIOMETER Action Set MTP2 (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1
Shared register parameter
This command is for fine tuning VMTP2 PM setting (use with BR=001) and is only valid when MTPC[3]=1. (40) SET MTP WRITE TIMER Action Set MTP3 (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 0
Shared register parameter
This command is only valid when MTPC[3]=1. (41) SET MTP READ TIMER Action Set MTP4 (Double-byte command) C/D W/R D7 0 0 0 0 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1
Shared register parameter
This command is only valid when MTPC[3]=1.
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
LCD VOLTAGE SETTING
MULTIPLEX RATES Multiplex Rate is completely software programmable in UC1697V via registers CEN, DST, DEN, FLT, FLB, and partial display control flags LC[9:8] and LC[0]. Combined with low power partial display mode and a low bias ratio of 6, UC1697V can support wide variety of display control options. For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power. BIAS RATIO SELECTION Bias Ratio (BR) is defined as the ratio between VLCD and VBIAS, i.e. BR = VLCD /VBIAS, where VBIAS = VB1+ - VB1- = VB0+ - VB0-. The theoretical optimum Bias Ratio can be estimated by Mux + 1 . BR of value 15~20% lower/higher than the optimum value calculated above will not cause significant visible change in image quality. Due to the nature of STN operation, an LCD designed for good gray-shade performance at high Mux Rate (e.g. MR=128), can generally perform very well as a black and white display, at lower Mux Rate. However, it is also true that such technique generally can not maintain LCD's quality of gray shade performance, since the contrast of the LCD will increase as Mux Rate decreases, and the shades near the two ends of the spectrum will start to lose visibility. UC1697V supports five BR as listed below. BR can be selected by software program. BR Bias Ratio 0 6 1 10 2 11 3 12 4 9 VLCD GENERATION VLCD may be supplied either by internal charge pump or by external power supply. The source of VLCD is controlled by PC[3:2]. When VLCD is generated internally, the voltage level of VLCD is determined by three control registers: BR (Bias Ratio), PM (Potentiometer), and TC (Temperature Compensation), with the following relationship:
V LCD = (CV 0 + C PM x PM ) x (1 + (T - 25) x CT %)
where CV0 and CPM are two constants, whose value depends on the setting of BR register, as illustrated in the table on the next page, PM is the numerical value of PM register, T is the ambient temperature in OC, and CT is the temperature compensation coefficient as selected by TC register. VLCD AND CONTRAST FINE TUNING Color STN LCD is sensitive to even a 0.5% mismatch between IC driving voltage and the VOP of LCD. It is very difficult for LCD makers to guarantee such high precision matching of parts from different venders. It is therefore necessary to adjust VLCD to precisely match the actual VOP of each LCD. For the best results, software or MTP based VLCD adjustment is the recommended method for VLCD fine tuning. System designers should always consider the contrast fine tuning requirement before finalizing on the LCM design. LOAD DRIVING STRENGTH FOR COG The power supply circuit of UC1697V is designed to handle LCD panels with loading up to ~16nF 2.8V. For using 7-/Sq ITO glass with VDD2/3 larger LCD panels, use lower resistance ITO glass. Due to crosstalk consideration, ~16nF is also the recommended maximum LCD panel loading for COG applications. Using 4.5-/Sq low resistance ITO glass for the IC bonding substrate can help improve image quality and operation tolerance. .
Table 1: Bias Ratios TEMPERATURE COMPENSATION Four different temperature compensation coefficients can be selected via software. The four coefficients are given below: TC % per C
o
0 -0.00
1 -0.10
2 -0.15
3 -0.05
Table 2: Temperature Compensation
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
VLCD QUICK REFERENCE
BR 6 10 11 12 9
CV0 (V) 6.402 10.670 11.737 12.804 9.603
CPM (mV) 13.14 21.90 24.09 26.28 19.71
PM_reg 0 255 0 255 0 198 0 141 0 255
VLCD (V) 6.40 9.75 10.67 16.25 11.74 16.51 12.80 16.51 9.60 14.63
VLCD-PM-BR relationship at 25oC
NOTE: 1. For good product reliability, please keep VLCD under 16.5V over all temperature. 2. The integer values of BR above are for reference only and may have slight shift.
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
HI-V GENERATOR REFERENCE CIRCUIT
VDD VB0+ VDD VB0VDD2/VDD3 VB1+ CB1 VDD2 VDD3 VB1CB0
UC1697V
VSS VSS2
VLCDOUT VLCDIN
CL RL (OPTIONAL)
FIGURE 1: Sample circuit using internal Hi-V generator circuit NOTE: Sample component values: (The illustrated circuit and component values are for reference only. Please optimize for specific requirements of each application.) CB0~1 : 2.2 F/5V or 300 x LCD load capacitance, whichever is higher. CL : 330 nF (25V) is appropriate for most applications. RL : 3.3~10 M to act as a draining circuit when VDD is shut down abruptly
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
LCD DISPLAY CONTROLS
CLOCK & TIMING GENERATOR UC1697V contains a built-in system clock. All required components for the clock oscillator are built-in. No external parts are required. Four different line rates are provided for system design flexibility. The line rate is controlled by register LC[4:3]. When Mux-Rate is above 88, frame rate is calculated as: Line-Rate = Frame Rate x Mux-Rate. When Mux-Rate is lowered to 87, 65, 44 and 33, line rate will be scaled down automatically by 1.5, 2, 3 and 4 times to reduce power consumption. Flicker-free frame rate is dependent on LC material and gray-shade modulation scheme. Line rate 30 Klps or higher is recommended for 32-shade mode. Choose lower frame rate for lower power, and choose higher frame rate to improve LCD contrast and minimize flicker. When switching from 32-shade modulation to On/Off mode, line rate will be scaled down automatically by ~30% to reduce power. Under most situations, flicker behavior is similar between these two modulation schemes. However, it is recommended to test each mode to make sure the result is as expected. DRIVER MODES COM and SEG drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]). When SEG drivers are in Idle mode, they will be connected together to ensure zero DC condition on the LCD. DRIVER ARRANGEMENTS The naming convention is COM(X), where X =1~128, referring to the COM driver for the X-th row of pixels on the LCD panel. The mapping of COM(x) to LCD pixel rows is fixed and it is not affected by SL, CST, CEN, DST, DEN, MX or MY settings. DISPLAY CONTROLS There are three groups of display control flags in the control register DC: Driver Enable (DE), AllPixel-ON (APO) and Inverse (PXV). DE has the overriding effect over PXV and APO. DRIVER ENABLE (DE) Driver Enable is controlled by the value of DC[2] via the Set Display Enable command. When DC[2] is set to OFF (logic "0"), both COM and SEG drivers will become idle and UC1697V will put itself into Sleep mode to conserve power. When DC[2] is set to ON, the DE flag will become "1", and UC1697V will first exit from Sleep mode, restore the power (VLCD, VD etc.) and then turn on COM and SEG drivers. ALL PIXELS ON (APO) When set, this flag will force all SEG drivers to output ON signals, disregarding the data stored in the display buffer. This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM. INVERSE (PXV) When this flag is set to ON, SEG drivers will output the inverse of the value it received from the display buffer RAM (bit-wise inversion). This flag has no impact on data stored in RAM. PARTIAL SCROLL Control register FLT and FLB specify two regions of rows which are not affected by the SL register. Since SL register can be used to implement scroll function. FLT and FLB registers can be used to implement fixed regions when the other part of the display is scrolled by SL. PARTIAL DISPLAY UC1697V provides flexible control of Mux Rate and active display area. Please refer to commands Set COM End, Set Partial Display Start, and Set Partial Display End for more detail. GRAY-SHADE MODULATION MODE UC1697V has two gray-shade modulation modes: 32-shade and On/Off mode. The On/Off mode will consume roughly 40~45% less power than the 32-shade mode, and can be used for situations where power consumption is more critical than color fidelity. Changing gray-shade modulation mode does not affect the content of SRAM display buffer, and the image data will remain the same after switching back and forth between On/Off mode and 32-shade mode.
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
INPUT COLOR FORMATS UC1697V supports the following two different input color formats. 256C (8-bit/RGB): In this color mode, R/G/B will be extended and the input data will be converted into 3R-3G-2B format before they are stored to display RAM. 4KC (12-bit/RGB): In this color mode, R/G/B will be extended and the input data will be converted into 5R-6G-5B format before they are stored to display RAM. 64KC (16-bit/RGB): This is the native color mode. Data will be stored directly to on-chip SRAM in 5R-6G-5B (16-bit) format (except shade1 and shade30, which are achieved by special dithering. See command Set Display Enable for more details). This is the default input format mode. Changing color mode does not affect the content already stored in the display buffer RAM. Users can mix several color modes together and switch among them in real time. For example, the menu portion can be painted in 4K-color mode for fast update speed, and then switch to 64K-color mode, together with window programming function to effectively produce smooth graphics images.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
ITO LAYOUT AND LC SELECTION
Since COM scanning pulses of UC1697V can be as short as 15S, it is critical to control the RC delay of COM and SEG signal to minimize crosstalk and maintain good mass production consistency. COM TRACES Excessive COM scanning pulse RC decay can cause fluctuation of contrast and increase COM direction crosstalk. Please limit the worst case of COM signals RC delay (RCMAX) as calculated below (RROW / 2.7 + RCOM) x CROW < 0.9S where CROW: LCD loading capacitance of one row of pixels. It can be calculated by CLCD/MuxRate, where CLCD is the LCD panel capacitance. RROW: ITO resistance over one row of pixels within the active area RCOM: COM routing resistance from IC to the active area + COM driver output impedance. In addition, please limit the min-max spread of RC decay to be: | RCMAX - RCMIN | < 0.22S so that the COM distortions on the top of the screen to the bottom of the screen are uniform. (Use worst case values for all calculations) SEG TRACES Excessive SEG signal RC decay can cause image dependent changes of medium gray shades and sharply increase of SEG direction crosstalk. For good image quality, please minimize SEG ITO trace resistance and limit the worst case of SEG signal RC delay as calculated below. (RCOL / 2.7 + RSEG) x CCOL < 0.25S where CCOL: LCD loading capacitance of one pixel column. It can be calculated by CLCD / #_column, where CLCD is the LCD panel capacitance. RCOL: ITO resistance over one column of pixels within the active area RSEG: SEG routing resistance from IC to the active area + SEG driver output impedance. (Use worst case values for all calculations) SELECTING LIQUID CRYSTAL The selection of LC material is crucial to achieve the optimum image quality of finished LCM. When (V90-V10)/V10 is too high, image contrast and color saturation will deteriorate, and images will look murky and dull. When (V90-V10)/V10 is too small, image contrast will become too strong, visibility of shades will suffer, and crosstalk may increase sharply for medium shades. For the best result, it is recommended the LC material has the following characteristics: (V90-V10)/V10 = (VON-VOFF)/VOFF x 0.72~0.80 where V90 and V10 are the LC characteristics, and VON and VOFF are the ON and OFF VRMS voltage produced by LCD driver IC at the specific Muxrate. Two examples are provided below: Duty 1/128 1/128 Bias 1/12 1/11 VON/VOFF -1 8.95% 8.85% x0.80 7.2% 7.1% x0.72 6.4% 6.4%
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High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
RAM W/R
POL
COM1
COM2
COM3
SEG1
SEG2
FIGURE 2: COM and SEG Driving Waveform
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
HOST INTERFACE
As summarized in the table below, UC1697V supports two parallel bus protocols, in either 8-bit or 16-bit bus width, and three serial bus protocols. Designers can either use parallel buses to achieve high data transfer rate, or use serial buses to create compact LCD modules. Bus Type S8 (4wr) 8-bit S8uc (3/4wr) Serial Write Only 00 11 S9 (3 wr)
8080 Width Access BM[1:0] {DB[15], DB[13]} CS[1:0] CD WR0 WR1 16-bit 10 Data
6800 8-bit 16-bit Read/Write 00 11 0x Data
Control & Data Pins
01 00 0x 10 Chip Select Control / Data
_ _
01 10 0
___
__
WR
___ __
R/W EN
0 0 - DB[8]=SDA, DB[0]=SCK
RD
DB[1,3,5,7,9,11] Data - Data - DB[0,2,4,6,8,10,12,14] Data Data Data Data * Connect unused control pins and data bus pins to VDD or VSS CS Disable Interface 16-bit 8-bit S8 or S9 S8uc * * * * * - CS Init bus state - - CD 1 0 Init bus state - - - CD 1 0 Init color mapping
RESET Init bus state
RESET Init color mapping
CS disable bus interface - CS can be used to disable Bus Interface Write / Read Access. CD refers to CD transitions within valid CS window. CD = 0 means write command or read status. CS Sync / RESET can be used to initialize bus state machine (like 8-bit / S8 / S9). RESET can be pin reset / soft reset / power on reset. CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping. Table 3: Host interfaces Summary
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High-Voltage Mixed-Signal IC
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PARALLEL INTERFACE The timing relationship between UC1697V internal control signal RD, WR and their associated bus actions are shown in the figure below. The Display RAM read interface is implemented as a two-stage pipe-line. This architecture requires that, every time memory address is modified, either in 8-bit mode or 16-bit mode, by either Set CA, or Set RA command, a dummy read cycle needs to be performed before the actual data can propagate through the pipe-line and be read from data port D. There is no pipeline in write interface of Display RAM. Data is transferred directly from bus buffer to internal RAM on the rising edges of write pulses. 16-BIT & 8-BIT BUS OPERATION UC1697V supports both 8-bit and 16-bit bus width. The bus width is determined by pin BM[1]. 8-bit bus operation exactly doubles the clock cycles of 16-bit bus operation, MSB followed by LSB, including the dummy read, which also requires two clock cycles. The bus cycle of 8-bit mode is reset each time CD pin changes state (when CS is active).
External CD ___ WR RD D[15:0] LLSB DL DL+K CMSB CLSB Dummy DC DC+1 MMSB MLSB
__
Internal Write Read Data Latch Column Address DL L L+K DL+K L+K+1 Dummy C DC C+1 DC+1 C+2 DC+2 C+3 M
FIGURE 3: 16-bit Parallel Interface & Related Internal Signals
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
SERIAL INTERFACE UC1697V supports three serial modes, a 4-wire SPI mode (S8), a compact 3/4-wire mode (S8uc), and a 3wire mode (S9). Bus interface mode is determined by the wiring of the BM[1:0], DB[15] and DB[13]. See table on last page for more detail. S8 (4-WIRE) INTERFACE Only write operations are supported in 4-wire serial mode. Pin CS[1:0] are used for chip select and bus cycle reset. Pin CD is used to determine the content of the data been transferred. During each write cycle, 8 bits of data, MSB first, are latched on eight rising SCK edges into an 8-bit data holder.
CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
If CD=0, the data byte will be decoded as command. If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM on the rising edge of the last SCK pulse. Pin CD is examined when SCK is pulled low for the LSB (D0) of each token.
FIGURE 4.a: 4-wire Serial Interface (S8) S8UC (3/4-WIRE) INTERFACE Only write operations are supported in this 3/4-wire serial mode. The data format is identical to S8. The CD pin transitions will reset the bus cycle in this
CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
mode. So, if CS pins are hardwired to enable chipselect, the bus can work properly with only three signal pins.
FIGURE 4.b: 3/4-wire Serial Interface (S8uc) S9 (3-WIRE) INTERFACE Only write operations are supported in this 3-wire serial mode. Pin CS[1-0] are used for chip select and bus cycle reset. On each write cycle, the first bit is CD, which determines the content of the following 8 bits of data, MSB first. These 8 command/data bits are latched on rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this
CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 CD D7 D6
8-bit will be treated as data and transferred to proper address in the Display Data RAM at the rising edge of the last SCK pulse. By sending CD information explicitly in the bit stream, control pin CD is not used, and should be connected to either VDD or VSS. The toggle of CS0 or CS1 for each byte of data/command is recommended but optional.
FIGURE 4.c: 3-wire Serial Interface (S9)
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HOST INTERFACE REFERENCE CIRCUIT
VDD
VCC
VDD
D15~D0
DB15~DB0
CD WR RD
CD WR0(WR) WR1(RD)
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
VDD
RST ID0 ID1
BM1 BM0
GND
VSS
FIGURE 5: 8080/16-bit parallel mode example
VDD
VDD VCC DB15 DB13 VDD
DB7~DB0 CD WR RD
DB7 ~ DB0 CD WR0(WR) WR1(RD)
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
RST ID0 ID1
BM1 BM0
GND
VSS
FIGURE 6: 8080/8-bit parallel mode example
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
VDD
VCC
VDD
D15-D0
DB15~DB0
CD R/W E
CD WR0(R/W) WR1(E)
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
VDD
RST ID0 ID1
BM1 BM0
GND
VSS
FIGURE 7: 6800/16-bit parallel mode example
VDD
VDD VCC DB15 DB13 VDD
DB7-DB0 CD R/W E
DB7 ~ DB0 CD WR0(R/W) WR1(E)
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
RST ID0 ID1
BM1 BM0
GND
VSS
FIGURE 8: 6800/8-bit parallel mode example
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VDD
VCC
DB15 DB13 SCK SDA CD SCK(DB0) SDA(DB8) CD WR0 WR1
VDD
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
RST ID0 ID1
BM1 BM0
GND
VSS
FIGURE 9: 4-Wires SPI (S8) serial mode example
VDD
VDD VCC DB15 DB13 SCK SDA CD SCK(DB0) SDA(DB8) CD WR0 WR1 CS0 VDD
MPU
VDD RST ID0 ID1 CS1 BM1 BM0
UC1697V
GND
VSS
FIGURE 10: 3/4-Wires SPI (S8uc) serial mode example
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
VDD
VDD VCC DB15 DB13 SCK SDA SCK(DB0) SDA(DB8) CD WR0 WR1 VDD
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1697V
RST ID0 ID1 VDD BM1 BM0
GND
VSS
FIGURE 11: 3/4-Wires SPI (S9) serial mode example
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DISPLAY DATA RAM
DATA ORGANIZATION The input display data (depend on color mode) are stored to a dual port static RAM (RAM, for Display Data RAM) organized as 128x128x16. After setting CA and RA, the subsequent data write cycles will store the data for the specified pixel to the proper memory location. Please refer to the map in the following page between the relation of COM, SEG, SRAM, and various memory control registers. DISPLAY DATA RAM ACCESS The Display RAM is a special purpose dual port RAM which allows asynchronous access to both its column and row data. Thus, RAM can be independently accessed both for Host Interface and for display operations. DISPLAY DATA RAM ADDRESSING A Host Interface (HI) memory access operation starts with specifying Row Address (RA) and Column Address (CA) by issuing Set Row Address and Set Column Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the end of row (127), and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when CA reaches the end of a row, CA will be reset to 0 and RA will increment or decrement, depending on the setting of row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0 or 127), RA will be wrapped around to the other end of RAM and continue. MX IMPLEMENTATION Column Mirroring (MX) is implemented by selecting either (CA) or (127-CA) as the RAM column address. Changing MX affects the data written to the RAM. Since MX has no effect on the data already stored in RAM, changing MX does not have immediate effect on the displayed pattern. To refresh the display, refresh the data stored in RAM after setting MX. ROW MAPPING COM electrode scanning orders are not affected by Scroll Line (SL), Fixed Line (FLT & FLB) or Mirror Y (MY, LC[3]). Visually, register SL having a non-zero value is equivalent to scrolling the LCD display up or down (depends on MY) by SL rows. RAM ADDRESS GENERATION The mapping of the data stored in the display SRAM and the scanning COM electrodes can be obtained by combining the fixed COM scanning sequence and the following RAM address generation formula. When FLT & FLB=0, during the display operation, the RAM line address generation can be mathematically represented as following: For the 1st line period of each field Line = SL Otherwise Line = Mod(Line+1, 128) Where Mod is the modular operator, and Line is the bit slice line address of RAM to be outputted to SEG drivers. Line 0 corresponds to the first bitslice of data in RAM. The above Line generation formula produces the "loop around" effect as it effectively resets Line to 0 when Line+1 reaches 128. Effects such as scrolling can be emulated by changing SL dynamically. MY IMPLEMENTATION Row Mirroring (MY) is implemented by reversing the mapping order between COM electrodes and RAM, i.e. the mathematical address generation formula becomes:
st For the 1 line period of each field Line = Mod(SL + MUX-1, 128) where MUX = CEN + 1
Otherwise Line = Mod(Line-1, 128) Visually, the effect of MY is equivalent to flipping the display upside down. The data stored in display RAM are not affected by MY.
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UC1697V
128x128RGB CSTN Controller-Driver
WINDOW PROGRAM Window program is designed for data-write in a specified window range of SRAM address. The procedure should start with window boundary registers setting (WPP0, WPP1, WPC0 and WPC1) and AC[3] setting for inside/outside window mode. When AC[3] is set to `0' (default value), data can be written to SRAM within the window address range which is specified by (WPP0, WPC0) and (WPP1, WPC1). When AC[3] is set to `1', data will be written to whole SRAM excluding the specified window area. The data-write direction will be determined by AC[2:0] and MX settings. When AC[0]=1, the Example1 (AC[2:0] = 001) : AC[3]=0 MX=0 column (0, 0)
(WPP0, WPC0)
data-write can be consecutive within the range of the specified window. AC[1] will control the data write in either column or row direction. AC[2] will result the data write starting either from row WPP0 or WPP1. MX is for the initial column address either from WPC0 to WPC1 or from (MCWPC0 to MC-WPC1). Specify the starting point of data-write by issuing commands Set Window Program Starting Column Address, and Set Window Program Starting Row Address.
Example 2 (AC[2:0] = 111) : AC[3] = 0 MX = 0 (127, 0)
(WPP0, WPC0)
row
(WPP1,WPC1)
(WPP1,WPC1)
(0, 127)
Example1-1 : AC[3]=1 MX=0 column 0
(WPP0, WPC0)
Example 2-1 : AC[3] = 1 MX = 0 (127, 0)
(WPP0, WPC0)
row
(WPP1,WPC1)
(WPP1,WPC1)
(0, 127)
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Row Adderss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH
RAM
MY=0 SL=0 SL=16 COM1 COM17 COM2 COM18 COM3 COM19 COM4 COM20 COM5 COM21 COM6 COM22 COM7 COM23 COM8 COM24 COM9 COM25 COM10 COM26 COM11 COM27 COM12 COM28 COM13 COM29 COM14 COM30 COM15 COM31 COM16 COM32 COM17 COM33 COM18 COM34 COM19 COM35 COM20 COM36 COM21 COM37 COM22 COM38 COM23 COM39 COM24 COM40 COM25 COM41 COM26 COM42 COM27 COM43 COM28 COM44 COM29 COM45
MY=1 SL=0 SL=16 COM128 COM 16 COM127 COM 15 COM126 COM 14 COM125 COM 13 COM124 COM 12 COM123 COM 11 COM122 COM 10 COM121 COM9 COM120 COM8 COM119 COM7 COM118 COM6 COM117 COM5 COM116 COM4 COM115 COM3 COM114 COM2 COM113 COM1 COM112 COM128 COM111 COM127 COM110 COM126 COM109 COM125 COM108 COM124 COM107 COM123 COM106 COM122 COM105 COM121 COM104 COM120 COM103 COM119 COM102 COM118 COM101 COM117 COM100 COM116
68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH SEG380 SEG381 SEG382 SEG383 SEG384
COM 105 COM 106 COM 107 COM 108 COM 109 COM 110 COM 111 COM 112 COM 113 COM 114 COM 115 COM 116 COM 117 COM 118 COM 119 COM 120 COM 121 COM 122 COM 123 COM 124 COM 125 COM 126 COM 127 COM 128
COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
COM 40 COM 39 COM 38 COM 37 COM 36 COM 35 COM 34 COM 33 COM 32 COM 31 COM 30 COM 29 COM 28 COM 27 COM 26 COM 25 COM 24 COM 23 COM 22 COM 21 COM 20 COM 19 COM 18 COM 17
SEG1
SEG2
SEG3
SEG4 SEG379
MX
SEG382
SEG383
SEG384
SEG380
SEG5
0
SEG5
SEG6
SEG1
SEG2
Example for memory mapping: let MX = 0, MY = 0, SL = 0, LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 64K-color ), according to the data shown in the above table (R: 11111b, G: 111111b, B: 11111b): st 1 byte of Write data: 11111111b 2nd byte of Write data: 11111111b
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SEG3
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
RESET & POWER MANAGEMENT
TYPES OF RESET UC1697V has two different types of Reset: Power-ON-Reset and System-Reset. Power-ON-Reset is performed right after VDD is connected to power. Power-On-Reset will first wait for about 150mS, depending on the time required for VDD to stabilize, and then trigger the System Reset. System Reset can also be activated by software command or by connecting RST pin to ground. In the following discussions, Reset means System Reset. RESET STATUS When UC1697V enters RESET sequence: * * Operation mode will be "Reset". All control registers are reset to default values. Refer to section Control Registers for details of their default values. CHANGING OPERATION MODE In addition to Power-ON-Reset, two commands will initiate OM transitions: Set Display Enable, and System Reset. When DC[2] is modified by Set Display Enable, OM will be updated automatically. There is no other action required to enter Sleep mode. OM changes are synchronized with the edges of UC1697V internal clock. To ensure consistent system states, wait at least 10S after Set Display Enable or System Reset command. Action Reset command RST_ pin pulled "L" Power ON reset Set Driver Enable to "0" Set Driver Enable to "1" Mode Reset Sleep Normal OM 00 10 11
Table 5: OM changes Both Reset mode and Sleep mode drain the charges stored in the external capacitors CB0, CB1, and CL. When entering Reset mode or Sleep mode, the display drivers will be disabled. The difference between Sleep mode and Reset mode is that, Reset mode clears all control registers and restores them to default values, while Sleep mode retains all the control registers values set by the user. It is recommended to use Sleep Mode for Display OFF operations as UC1697V consumes very little energy in Sleep mode (typically under 2A). EXITING SLEEP MODE UC1697V contains internal logic to check whether VLCD and VBIAS are ready before releasing COM and SEG drivers from their idle states. When exiting Sleep or Reset mode, COM and SEG drivers will not be activated until UC1697V internal voltage sources are restored to their proper values.
OPERATION MODES UC1697V has three operating modes (OM): Reset, Sleep, Normal. Mode OM Host Interface Clock LCD Drivers Charge Pump Draining Circuit Reset 00 Active OFF OFF OFF ON Sleep Normal 10 Active OFF OFF OFF ON 11 Active ON ON ON OFF
Table 4: Operating Modes
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(c)1999 ~ 2007 POWER-DOWN SEQUENCE To prevent the charge stored in capacitors CBX and CL from damaging the LCD, when VDD is switched off, use Reset mode to enable the built-in draining circuit and discharge these capacitors. The draining resistor is 10 K for both VLCD and VB+. It is recommended to wait 3 x RC for VLCD and 1.5 x RC for VB. For example, if CL is 0.1uF, then the draining time required for VLCD is ~3 mS. When internal VLCD is not used, UC1697V will NOT drain VLCD during RESET. System designers need to make sure external VLCD source is properly drained off before turning off VDD.
POWER-UP SEQUENCE UC1697V power-up sequence is simplified by builtin "Power Ready" flags and the automatic invocation of System-Reset command after PowerON-Reset. System programmers are only required to wait 150 mS before the CPU starting to issue commands to UC1697V. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands. There's no delay needed while turning on VDD and VDD2/3, and either one can be turned on first.
Figure 13: Reference Power-Down Sequence
Figure 12: Reference Power-Up Sequence
Either VDD or VDD2/3 may be turned on first. VDD2/3 2.6V VDD 1.8V VDD2/3 VDD
TWait > 10mS VDD < 0.1V
Tf < 10 mS
10S < T1< 10 mS
Figure 14: Power Off-On Sequence
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
MULTI-TIME PROGRAM NV MEMORY
OVERVIEW MTP feature is available for UC1697V such that LCM makers can record an PM offset value in non-volatile memory cells, which can then be used to adjust the effective VLCD value, in order to achieve high level of consistency for LCM contrast across all shipments. To accomplish this purpose, three operations are supported by UC1697V: MTP-Erase, MTP-Program, MTP-Read. MTP-Program requires an external power source supplied to TST4 pin. MTP allows to program at least 10 times and should be performed only by the LCM makers. MTP-Read is facilitated by the internal DC-DC converter built-in on UC1697V, no external power source is required, and it is performed automatically after hardware RESET (power-ON or pin RESET). OPERATION FOR THE SYSTEM USERS For the MTP version of UC1697V, the content of the NV memory will be read automatically after the power-on and hardware pin RESET. There is no user intervention or external power source required. When set up properly, the VLCD will be fine tuned to achieve high level of consistency for the LCM contrast. The MTP-READ is a relatively slow process and the time required can vary quite a bit. For a successful MTP-READ operation, the MS and WS bits in the Read Status commands will exhibit the following waveforms. RST 150mS Although user can use Read Status command in a polling loop to make sure {MS, WS}={0, 1} before proceeding with the normal operations, however, it may be simpler to just issue Set Display Enable command every 0.5~2 second, repeatedly, together with other LCM optimization settings, such as BR, CEN, TC, etc. The above "Periodical re-initializing" approach is also an effective safeguard against accidental display off events such as * * ESD strikes Mechanical shocks causing LCM connector to malfunction temporarily
HARDWARE VS. SOFTWARE RESET The auto-MTP-READ is only performed for hardware RESET (power-ON and RST pin), but not for software RESET command. This enables the ICs to turn on display faster without the delay caused by MTP-READ. It is recommended to use software RESET for normal operation control purpose and hardware RESET only during the event of power up and power down. OPERATION FOR THE LCM MAKERS Always ERASE the MTP NV memory cells, before starting the Write process.
MS
WS As illustrated above, the {MS, WS} will go through a {0,0} {1,0} {1,1} {0,1} transition. When the {MS, WS}={0,1} state is reached, it means the LCM is ready to be turned on.
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MTP OPERATION FOR LCM MAKERS
1. High voltage supply and timer setting In MTP Program operation, two different high voltages are needed. In chip design, one high voltage is generated by internal charge pump (VLCD), the other high voltage must be input from TST4 by external voltage source. VLCD value is controlled by register MTP3 and MTP2. The default values of these two registers are appropriate for most applications. External TST4 power source is required for MTP Program operation. MTP Programming speed depends on the TST4 voltage. Considering the ITO trace resistance in COG modules, it is recommended to program the MTP cells one at a time, so that the required 10V at TST4 can be maintained with proper consistency. No external power source is required for MTP Erase and Read operation. For these MTP operations, TST4 should be open, or connected to VDD3. VLCD Program Erase Read MTP3 : 3Dh (12V) MTP3 : 3Dh (12V) MTP2 : 00h (6.4V) TST4 (external input) 10V (1mA per bit) Floating or VDD3 Floating or VDD3
Note: 1. 2. Do Erase before Program and program one bit at a time. When doing MTP Program or Erase, it's required to use VDD2/3 3.0V.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
3.
Read MTP status bits
With normal Get Status method (CD=0, W/R=1), MTP operation status can be monitored in the real time. There are 3 status bits (WS, MD, MS) in status register. MTP control circuit will read to verify if the operation (program, erase) success or not. If the operation succeeded, and current operation will be ended with WS=1. If it failed, last operation will be automatically retried two more times. If it fails 3 times, WS will be set to 0 and the operation is aborted. MD is MTP ID, which is either 1 for MTP IC. No transition.
Program: 10 V TST4 Erase: VDD3
Program/Erase
VLCD=12V
Read to verify
VLCD=6.4V
VLCD MTP Command MD MS WS MTP status bits, TST4 & VLCD Waveform may repeat 3 times
MTP CELL VALUE USAGE There are 6 MTP cell bits. They are divided into two groups for different purpose. MTP[5:0] : VLCD Trim When PMO[5]=1: PM with trim = PM - PMO[4:0] When PMO[5]=0: PM with trim = PM + PMO[4:0]
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MTP COMMAND SEQUENCE SAMPLE CODES The following tables are examples of command sequence for MTP Program and Erase operations. These are only to demonstrate some "typical, generic" scenarios. Designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences are for their specific design needs. MTP operations (Erase, Program, Read) and Set Display ON is mutual exclusive. There is no harm done to the IC or the LCM if this is violated. However, the violating commands will be ignored. Type Required: Customized: Advanced: Optional: These items are required These items are not necessary if customer parameters are the same as default We recommend new users to skip these commands and use default values. These commands depend on what users want to do.
C/D W/R (1)
The type of the interface cycle. It can be either Command (0) or Data (1) The direction of dataflow of the cycle. It can be either Write (0) or Read (1). MTP Program Sample Code Chip Action Set Line Rate Set VMTP1 Potentiometer Set VMTP2 Potentiometer Set MTP Write Timer Set MTP Read Timer Set MTP Write Mask Comments Set LC[4:3]=11b Set MTP VLCD MTP2: 00h(6.4V) Set MTP VLCD MTP3: 3Dh(12V) Set MTP Timer MTP4: 50h(100mS) Set MTP Timer MTP5: 08h(10mS) Set MTP Bit Mask Ex: To program MTPM[0] to be 1, set the value to 00000001b * Apply TST4 voltage Program: 10V Set MTPC[3]=1 Set MTPC[2:0]=011 Check MTP Status until MS=0, WS=1 Remove TST4 voltage Power OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R R R C R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1
1 MTPM 0 Set MTP Control 1
- WS - MS Get Status & PM VDD=0V
* It is recommended that users program one bit at a time.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
(2)
MTP Erase Sample Code Chip action Set Line Rate Set VMTP1 Potentiometer Set VMTP2 Potentiometer Set MTP Write Timer Set MTP Read Timer Set MTP Write Mask Comments Set LC[4:3]=11b Set MTP VLCD MTP2: 00h(6.4V) Set MTP VLCD MTP3: 3Dh(12V) Set MTP Timer MTP4: 50h(100mS) Set MTP Timer MTP5: 08h(10mS) Set MTP Bit Mask Ex: To erase MTPM[3:0], set the value to 00001111b Set MTPC[3]=1 Set MTPC[2:0]=010 Check MTP Status until MS=0 WS=1 Power OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R R R C R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1
1 MTPM1 0 Set MTP Control 0
- WS - MS Get Status & PM
R VDD=0V Note: It is recommended that users clear first all the bits to be programmed.
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SAMPLE POWER MANAGEMENT COMMAND SEQUENCES The following tables are examples of command sequence for power-up, power-down and display ON/OFF operations. These are only to demonstrate some "typical, generic" scenarios. Designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences are for their specific design needs. C/D W/R Type The type of the interface cycle. It can be either Command (0) or Data (1) The direction of dataflow of the cycle. It can be either Write (0) or Read (1). Required: These items are required Customized: These items are not necessary if customer parameters are the same as default We recommend new users to skip these commands and use default values. Advanced: Optional: These commands depend on what users want to do.
POWER-UP Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R R R C C A C C R - - - - 0 0 0 0 0 0 0 1 . . 1 0 - - - - 0 0 0 0 0 0 0 0 . . 0 0 - - - - 0 1 1 1 1 1 # # . . # 1 - - - - 0 1 0 1 1 0 # # . . # 0 - - - - 1 0 1 0 1 0 # # . . # 1 - - - - 0 0 0 1 0 0 # # . . # 0 - - - - 0 0 0 0 1 0 # # . . # 1 - - - - 1 # 0 1 0 0 # # . . # 1 - - - - # # # # # 0 # # . . # 1 - - - - # # # # # Chip action Turn on VDD and VDD2/3 Set RST pin Low Set RST pin High Automatic Power-ON Reset Set Temp. Compensation Set LCD Mapping Set Line Rate Set Color Mode Set LCD Bias Ratio Comments Wait until VDD, VDD2/3 are stable Wait 1mS after RST is Low Wait 150mS Set up LCD format specific parameters, MX, MY, etc. Fine tune for power, flicker, contrast, and shading. LCD specific operating voltage setting LCD specific operating voltage setting Set up display image
O R
1 Set VBIAS Potentiometer # # . Write display RAM . # 1 Set Display Enable
POWER-DOWN Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R 0 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 1 - Chip action Comments Wait ~3mS before VDD OFF 0 System Reset - Draining capacitor
DISPLAY-OFF Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R C 0 1 . . 1 0 0 0 . . 0 0 1 # . . # 1 0 # . . # 0 1 # . . # 1 0 # . . # 0 1 # . . # 1 1 # . . # 1 1 # . . # 1 Chip action Comments Set up display image (Image update is optional. Data in the RAM is retained through the SLEEP state.) 0 Set Display Disable # Write display RAM . . # 1 Set Display Enable
R
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
ESD CONSIDERATION
UC1600 series products usually are provided in bare die format to customers. This makes the product particularly sensitive to ESD damage during handling and manufacturing process. It is therefore highly recommended that LCM makers strictly follow the "JESD 625-A Requirements for Handling ElectrostaticDischarge-Sensitive (ESDS) Devices" when manufacturing LCM. The following pins in UC1697V require special "ESD Sensitivity" consideration in particular: Test Mode LCD Driver LCM Interface TST1/2/4 LCM HV pin/ Test pin CB pins VLCDIN VLCDOUT PWR / GND Machine Mode VDD 200V 300V 300V 300V 300V 300V -VSS 200V 300V 300V 300V 300V 300V 300V Human Body Mode VDD 2.0KV 3.0KV 3.0KV 3.0KV 3.0KV 3.0KV -VSS 2.0KV 3.0KV 3.0KV 3.0KV 3.0KV 3.0KV 3.0KV
According to UltraChip's Mass Production experiences, the ESD tolerance conditions are believed to be very stable and can produce high yield in multiple customer sites. However, special care is still required during handling and manufacturing process to avoid unnecessary yield loss due to ESD damages.
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ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134, Note 1 and 2 Symbol VDD VDD2 VDD3 VDD2/3-VDD VLCD VIN TOPR TSTR Logic Supply voltage LCD Generator Supply voltage Analog Circuit Supply voltage Voltage difference between VDD and VDD2/3 LCD Driving voltage Digital input signal Operating temperature range Storage temperature Parameter Min. -0.3 -0.3 -0.3 --0.3 -0.4 -30 -55 Max. +4.0 +4.0 +4.0 1.6 +19.8 VDD + 0.5 +85 +125 Unit V V V V V V
o o
C C
NOTE:
1. 2. VDD is based on VSS = 0V Stress beyond ranges listed above may cause permanent damages to the device.
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ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
SPECIFICATIONS
DC CHARACTERISTICS Symbol VDD VDD2/3 VLCD VD VIL VIH VOL VOH IIL ISB CIN COUT RON(SEG) Parameter Supply for digital circuit Supply for bias & pump Charge pump output LCD data voltage Input logic LOW Input logic HIGH Output logic LOW Output logic HIGH Input leakage current Standby current Input capacitance Output capacitance SEG output impedance VLCD = 16.5V VLCD = 16.5V LC[4:3] = 10b, 25 C
O
Conditions
Min. 1.65 2.5
Typ.
Max. 3.3 3.3
Unit V V V V V V V V A A PF PF Klps
VDD2/3 = 2.8V, 25 C VDD2/3 = 2.8V, 25 C
O
O
15.2 0.93 0.8VDD
16.5 1.76 0.2VDD 0.2VDD
0.8VDD 1.5 VDD = VDD2/3 = 3.3V, Temp = 85oC 5 5 1000 1000 1900 -10% 29.6 50 10 10 1200 1200 2500 +10%
RON(COM) Upward COM output impedance Average line rate
RONs(COM) Downward COM output impedance VLCD = 16.5V fLINE
Note : Voltages exceeding the Max. value may still keep the IC operating properly, yet might shorten its lifetime.
POWER CONSUMPTION VDD = 2.7 V, VLCD = 15.22 V, Mux Rate = 128, CB = 2.2 F, N-line inversion = 17 lines Display Pattern All-Pixel-OFF 2-pixel checker None Bias Ratio = 12, Line Rate = 10 b, Bus mode = 6800, Temperature = 25 oC, Color Mode = 64 K mode, Conditions Bus = idle Bus = idle Reset (stand-by current) PM = 92, Panel Loading (PC[1:0]) = 11 b, CL = 330 nF, MTP= 00 H, All HV outputs are open circuit. Typ. (A) 1233 1692 <1 Max. (A) (TBD) (TBD) 5
Revision A_0.6
57
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
AC CHARACTERISTICS
CD CS0 CS1 tAS80 tCSSA80 WR0 WR1 Write D[7:0] tACC80 Read D[7:0] FIGURE 15: Parallel Bus Timing Characteristics (for 8080 MCU)
o
tAH80 tCY80 tCSH80 tHPW80
tPWR80, tPWW80
tDS80
tDH80
tOD80
(2.5V
VDD< 3.3V, Ta= -30 to +85 C) Signal CD Description Address setup time Address hold time System cycle time 16-bit bus (read) (write) 8-bit bus (read) (write) Pulse width 16-bit (read) 8-bit Pulse width 16-bit (write) 8-bit High pulse width 16-bit bus (read) (write) 8-bit bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 0 170 130 100 80 85 50 65 40 85 65 50 40 30 0 - 15 0 0 Max. - - Units nS nS
Symbol tAS80 tAH80 tCY80
tPWR80 tPWW80 tHPW80
WR1 WR0 WR0, WR1
- - -
nS nS nS
tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSH80
D0~D15
- 60 30
nS nS nS
CL = 100pF
CS1/CS0
58
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
o
(1.65V
VDD< 2.5V, Ta= -30 to +85 C) Signal CD Description Address setup time Address hold time System cycle time 16-bit bus (read) (write) 8-bit bus (read) (write) Pulse width 16-bit (read) 8-bit (read) Pulse width 16-bit (write) 8-bit (write) High pulse width 16-bit bus (read) (write) 8-bits bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 0 320 270 180 145 160 90 135 72 160 135 90 72 60 0 30 0 0 Max. - - Units nS nS
Symbol tAS80 tAH80 tCY80
tPWR80 tPWW80 tHPW80
WR1 WR0
- - -
nS nS nS
WR0, WR1 tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSH80
D0~D15
- 120 60
nS nS nS
CL = 100pF
CS1/CS0
Revision A_0.6
59
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
CD CS0 CS1 tAS68 tCSSA68 tCY68 tPWR68, tPWW68 WR1 tDS68 Write D[7:0] tACC68 Read D[7:0] FIGURE 16: Parallel Bus Timing Characteristics (for 6800 MCU)
o
tAH68 tCSH68 tLPW68
tDH68
tOD68
(2.5V
VDD< 3.3V, Ta= -30 to +85 C) Signal CD Description Address setup time Address hold time System cycle time 16-bit bus (read) (write) 8-bit bus (read) (write) Pulse width 16-bit (read) 8-bit Pulse width 16-bit (write) 8-bit Low pulse width 16-bit bus (read) (write) 8-bit bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 0 170 130 100 80 85 50 65 40 85 65 50 40 30 0 - 15 0 0 Max. - - Units nS nS
Symbol tAS68 tAH68 tCY68
tPWR68 tPWW68 tLPW68
WR1
- - -
nS nS nS
tDS68 tDH68 tACC68 tOD68 tCSSA68 tCSH68
D0~D7
- 60 30
nS nS nS
CL = 100pF
CS1/CS0
60
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
o
(1.65V
VDD< 2.5V, Ta= -30 to +85 C) Signal CD Description Address setup time Address hold time System cycle time 16-bit bus (read) (write) 8-bit bus (read) (write) Pulse width 16-bit (read) 8-bit (read) Pulse width 16-bit (write) 8-bit (write) Low pulse width 16-bit bus (read) (write) 8-bit bus (read) (write) Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 0 0 320 270 180 145 160 90 135 72 160 135 90 72 60 0 30 0 0 Max. - - Units nS nS
Symbol tAS68 tAH68 tCY68
tPWR68 tPWW68 tLPW68
WR1
- - -
nS nS nS
tDS68 tDH68 tACC68 tOD68 tCSSA68 tCSH68
D0~D7
- 120 60
nS nS nS
CL = 100pF
CS1/CS0
Revision A_0.6
61
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
CD CS0 CS1 tASS8 tCSSAS8 tCYS8 tLPWS8 SCK tDSS8 SDA FIGURE 17: Serial Bus Timing Characteristics (for S8/S8uc)
o
tAHS8 tCSHS8 tHPWS8
tDHS8
(2.5V
VDD< 3.3V, Ta= -30 to +85 C) Signal CD SCK Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 0 0 40 20 20 15 0 5 5 Max. - - - - - - Units nS nS nS nS nS nS nS
Symbol tASS8 tAHS8 tCYS8 tLPWS8 tHPWS8 tDSS8 tDHS8 tCSSAS8 tCSHS8 (1.65V
SDA CS1/CS0
VDD< 2.5V, Ta= -30 to +85 C) Signal CD SCK Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 0 0 75 37 37 30 10 15 15 Max. - - - - - - Units nS nS nS nS nS nS nS
o
Symbol tASS8 tAHS8 tCYS8 tLPWS8 tHPWS8 tDSS8 tDHS8 tCSSAS8 tCSHS8
SDA CS1/CS0
62
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
CS0 CS1 tCSS9 tCYS9 tWLS9 SCK tDSS9 SDA tDHS9 tWHS9 tCSHS9
FIGURE 18: Serial Bus Timing Characteristics (for S9)
o
(2.5V
VDD< 3.3V, Ta= -30 to +85 C) Signal SCK Description System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 40 20 15 15 0 5 5 Max. - - - - Units nS nS nS nS nS
Symbol tCYS9 tLPWS9 tHPWS9 tDSS9 tDHS9 tCSSAS9 tCSHS9 (1.65V
SDA CS1/CS0
VDD< 2.5V, Ta= -30 to +85 C) Signal SCK Description System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 75 40 30 30 0 10 10 Max. - - - - Units nS nS nS nS nS
o
Symbol tCYS9 tLPWS9 tHPWS9 tDSS9 tDHS9 tCSSAS9 tCSHS9
SDA CS1/CS0
Revision A_0.6
63
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
t RW RS T t RD WR[1:0]
FIGURE 19: Reset Characteristics
o
(1.65V
VDD< 3.3V, Ta= -30 to +85 C) Signal RST RST, WR Description Reset low pulse width Reset to WR pulse delay Condition Min. 3 10 Max. - - Units S mS
Symbol tRW tRD
64
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
PHYSICAL DIMENSIONS
PAD COORDINATES DIE SIZE:
11309.6 M x 1273 M 40 M
DIE THICKNESS:
400 M 20 M
AU BUMP HEIGHT:
15 M (HMAX-HMIN) within die 2 M
BUMP SIZE: SEG /COM: 14.5x138 M2 BUMP PITCH:
26.5 M
BUMP GAP:
12.0 M
PAD COORDINATE ORIGIN:
Chip center
(Drawing and coordinates are for the Circuit/Bump view.)
Revision A_0.6
65
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
ALIGNMENT MARK INFORMATION U-Left Mark U-Right Mark
(0,0)
D-Left Mark
SHAPE OF THE ALIGNMENT MARK:
1 2 3 2 3 1 3 1 C 2 4
D-Right Mark
NOTE: Alignment marks are on Metal3 under Passivation. The "x" and "+" marks are symmetric both horizontally and vertically.
COORDINATES:
U-Left Mark (L) X 1 2 3 Y U-Right Mark (X) X Y
-5374.5 -5363.3 -5346.5
586 569.2 558
5346.5 5374.5 5353.5
586 558 586
D-Left Mark (+) X 1 2 3 4 C Y
D-Right Mark (+) X Y
-5419.8 -495 5399.8 -495 -5399.8 -580 5419.8 -580 -5452.3 -527.5 5367.3 -527.5 -5367.3 -547.5 5452.3 -547.5 -5409.8 -537.5 5409.8 -537.5 Note: The values of x-coordinate and y-coordinate in the tables are after-rounded.
TOP METAL AND PASSIVATION:
SiON / 10.5KA Metal3 / 9KA FOR MTP PROCESS CROSS-SECTION
66
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
PAD COORDINATES
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pad DUMMY COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 COM64 COM66 COM68 COM70 COM72 COM74 COM76 COM78 COM80 COM82 COM84 COM86 COM88 COM90 COM92 COM94 COM96 COM98 COM100 COM102 COM104 DUMMY COM106 COM108 COM110 COM112 COM114 COM116 COM118 COM120 COM122 COM124 COM126 COM128 D15 VDDX D14 D13 D12 D11 X -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5551.3 -5325.05 -5298.55 -5272.05 -5245.55 -5219.05 -5192.55 -5166.05 -5139.55 -5113.05 -5086.55 -5060.05 -5033.55 -4853.9 -4793.9 -4733.9 -4487.9 -4427.9 -4181.9 Y 587.375 556.5 530 503.5 477 450.5 424 397.5 371 344.5 318 291.5 265 238.5 212 185.5 159 132.5 106 79.5 53 26.5 0 -26.5 -53 -79.5 -106 -132.5 -159 -185.5 -212 -238.5 -265 -291.5 -318 -344.5 -371 -397.5 -424 -450.5 -477 -503.5 -530 -556.5 -587.375 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 W 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 45 45 45 45 45 45 H 23.25 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 23.25 138 138 138 138 138 138 138 138 138 138 138 138 119 119 119 119 119 119 # 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pad D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RST_ WR0 VDDX WR1 CD CS0 VDDX CS1 BM0 VDDX BM1 TST4 TST4 TST1 TST2 ID0 VDDX ID1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DUMMY VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VDD VDD VDD VDD VDD VDD VDD DUMMY DUMMY X -4121.9 -3875.9 -3815.9 -3569.9 -3509.9 -3263.9 -3203.9 -2957.9 -2897.9 -2651.9 -2591.9 -2415.1 -2333.5 -2253.7 -2173.9 -2092.3 -2010.7 -1930.9 -1851.1 -1769.5 -1689.7 -1609.9 -1530.1 -1470.1 -1059.225 -999.225 -818.8 -739 -659.2 -579.4 -519.4 -459.4 -399.4 -339.4 -279.4 -219.4 -159.4 -99.4 -39.4 20.6 80.6 140.6 228.775 313.6 373.6 433.6 493.6 553.6 613.6 673.6 733.6 793.6 853.6 913.6 973.6 1033.6 1093.6 1153.6 1213.6 1273.6 1333.6 1519.525 1579.525 Y -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541 -541 -541.5 -541 -541 -541 -541.5 -541 -541 -541.5 -541 -541.5 -541.5 -541.5 -541.5 -541 -541.5 -541 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 W 45 45 45 45 45 45 45 45 45 45 45 65 65 45 65 65 65 45 65 65 45 65 45 45 45 45 65 45 65 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 H 119 119 119 119 119 119 119 119 119 119 119 118 118 119 118 118 118 119 118 118 119 118 119 119 119 119 118 119 118 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119
Revision A_0.6
67
ULTRACHIP
High-Voltage Mixed-Signal IC # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Pad DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 DUMMY VDD3 VDD3 VB0+ VB0+ VB0+ VB0+ VB1+ VB1+ VB1+ VB1+ VB1VB1VB1VB1VB0VB0VB0VB0VLCDIN VLCDIN VLCDOUT VLCDOUT COM127 COM125 COM123 COM121 COM119 COM117 COM115 COM113 COM111 COM109 COM107 COM105 DUMMY COM103 COM101 COM99 COM97 COM95 COM93 COM91 COM89 COM87 COM85 COM83 COM81 COM79 COM77 COM75 COM73 X 1639.525 1699.525 1759.525 1819.525 1879.525 1939.525 2125.45 2185.45 2245.45 2305.45 2365.45 2425.45 2485.45 2573.625 2750.3 2810.3 2878.45 2938.45 2998.45 3058.45 3266.6 3326.6 3386.6 3446.6 3654.75 3714.75 3774.75 3834.75 4042.9 4102.9 4162.9 4222.9 4562.9 4622.9 4682.9 4742.9 5033.55 5060.05 5086.55 5113.05 5139.55 5166.05 5192.55 5219.05 5245.55 5272.05 5298.55 5325.05 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 Y -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -541.5 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -533 -587.375 -556.5 -530 -503.5 -477 -450.5 -424 -397.5 -371 -344.5 -318 -291.5 -265 -238.5 -212 -185.5 -159 W 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 H 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 119 138 138 138 138 138 138 138 138 138 138 138 138 23.25 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 # 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Pad COM71 COM69 COM67 COM65 COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 DUMMY COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 X 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5551.3 5313.25 5286.75 5260.25 5233.75 5207.25 5180.75 5154.25 5127.75 5101.25 5074.75 5048.25 5021.75 4995.25 4968.75 4942.25 4915.75 4889.25 4862.75 4836.25 4809.75 4783.25 4756.75 4730.25 4703.75 4677.25 4650.75 4624.25 4597.75 4571.25 4544.75 4518.25 4491.75 4465.25 4438.75 4412.25 4385.75 4359.25 Y -132.5 -106 -79.5 -53 -26.5 0 26.5 53 79.5 106 132.5 159 185.5 212 238.5 265 291.5 318 344.5 371 397.5 424 450.5 477 503.5 530 556.5 587.375 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
(c)1999 ~ 2007
W 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 H 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 23.25 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
68
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
# 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321
Pad SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93
X 4332.75 4306.25 4279.75 4253.25 4226.75 4200.25 4173.75 4147.25 4120.75 4094.25 4067.75 4041.25 4014.75 3988.25 3961.75 3935.25 3908.75 3882.25 3855.75 3829.25 3802.75 3776.25 3749.75 3723.25 3696.75 3670.25 3643.75 3617.25 3590.75 3564.25 3537.75 3511.25 3484.75 3458.25 3431.75 3405.25 3378.75 3352.25 3325.75 3299.25 3272.75 3246.25 3219.75 3193.25 3166.75 3140.25 3113.75 3087.25 3060.75 3034.25 3007.75 2981.25 2954.75 2928.25 2901.75 2875.25 2848.75 2822.25 2795.75 2769.25 2742.75 2716.25 2689.75 2663.25 2636.75
Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5
H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
# 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386
Pad SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158
X 2610.25 2583.75 2557.25 2530.75 2504.25 2477.75 2451.25 2424.75 2398.25 2371.75 2345.25 2318.75 2292.25 2265.75 2239.25 2212.75 2186.25 2159.75 2133.25 2106.75 2080.25 2053.75 2027.25 2000.75 1974.25 1947.75 1921.25 1894.75 1868.25 1841.75 1815.25 1788.75 1762.25 1735.75 1709.25 1682.75 1656.25 1629.75 1603.25 1576.75 1550.25 1523.75 1497.25 1470.75 1444.25 1417.75 1391.25 1364.75 1338.25 1311.75 1285.25 1258.75 1232.25 1205.75 1179.25 1152.75 1126.25 1099.75 1073.25 1046.75 1020.25 993.75 967.25 940.75 914.25
Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5
H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
Revision A_0.6
69
ULTRACHIP
High-Voltage Mixed-Signal IC # 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 Pad SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178 SEG179 SEG180 SEG181 SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 SEG214 SEG215 SEG216 SEG217 SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 X 887.75 861.25 834.75 808.25 781.75 755.25 728.75 702.25 675.75 649.25 622.75 596.25 569.75 543.25 516.75 490.25 463.75 437.25 410.75 384.25 357.75 331.25 304.75 278.25 251.75 225.25 198.75 172.25 145.75 119.25 92.75 66.25 39.75 13.25 -13.25 -39.75 -66.25 -92.75 -119.25 -145.75 -172.25 -198.75 -225.25 -251.75 -278.25 -304.75 -331.25 -357.75 -384.25 -410.75 -437.25 -463.75 -490.25 -516.75 -543.25 -569.75 -596.25 -622.75 -649.25 -675.75 -702.25 -728.75 -755.25 -781.75 -808.25 Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 # 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 Pad SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 SEG240 SEG241 SEG242 SEG243 SEG244 SEG245 SEG246 SEG247 SEG248 SEG249 SEG250 SEG251 SEG252 SEG253 SEG254 SEG255 SEG256 SEG257 SEG258 SEG259 SEG260 SEG261 SEG262 SEG263 SEG264 SEG265 SEG266 SEG267 SEG268 SEG269 SEG270 SEG271 SEG272 SEG273 SEG274 SEG275 SEG276 SEG277 SEG278 SEG279 SEG280 SEG281 SEG282 SEG283 SEG284 SEG285 SEG286 SEG287 SEG288 X -834.75 -861.25 -887.75 -914.25 -940.75 -967.25 -993.75 -1020.25 -1046.75 -1073.25 -1099.75 -1126.25 -1152.75 -1179.25 -1205.75 -1232.25 -1258.75 -1285.25 -1311.75 -1338.25 -1364.75 -1391.25 -1417.75 -1444.25 -1470.75 -1497.25 -1523.75 -1550.25 -1576.75 -1603.25 -1629.75 -1656.25 -1682.75 -1709.25 -1735.75 -1762.25 -1788.75 -1815.25 -1841.75 -1868.25 -1894.75 -1921.25 -1947.75 -1974.25 -2000.75 -2027.25 -2053.75 -2080.25 -2106.75 -2133.25 -2159.75 -2186.25 -2212.75 -2239.25 -2265.75 -2292.25 -2318.75 -2345.25 -2371.75 -2398.25 -2424.75 -2451.25 -2477.75 -2504.25 -2530.75 Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
(c)1999 ~ 2007
W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
70
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
# 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581
Pad SEG289 SEG290 SEG291 SEG292 SEG293 SEG294 SEG295 SEG296 SEG297 SEG298 SEG299 SEG300 SEG301 SEG302 SEG303 SEG304 SEG305 SEG306 SEG307 SEG308 SEG309 SEG310 SEG311 SEG312 SEG313 SEG314 SEG315 SEG316 SEG317 SEG318 SEG319 SEG320 SEG321 SEG322 SEG323 SEG324 SEG325 SEG326 SEG327 SEG328 SEG329 SEG330 SEG331 SEG332 SEG333 SEG334 SEG335 SEG336 SEG337 SEG338 SEG339 SEG340 SEG341 SEG342 SEG343 SEG344 SEG345 SEG346 SEG347 SEG348 SEG349 SEG350 SEG351 SEG352 SEG353
X -2557.25 -2583.75 -2610.25 -2636.75 -2663.25 -2689.75 -2716.25 -2742.75 -2769.25 -2795.75 -2822.25 -2848.75 -2875.25 -2901.75 -2928.25 -2954.75 -2981.25 -3007.75 -3034.25 -3060.75 -3087.25 -3113.75 -3140.25 -3166.75 -3193.25 -3219.75 -3246.25 -3272.75 -3299.25 -3325.75 -3352.25 -3378.75 -3405.25 -3431.75 -3458.25 -3484.75 -3511.25 -3537.75 -3564.25 -3590.75 -3617.25 -3643.75 -3670.25 -3696.75 -3723.25 -3749.75 -3776.25 -3802.75 -3829.25 -3855.75 -3882.25 -3908.75 -3935.25 -3961.75 -3988.25 -4014.75 -4041.25 -4067.75 -4094.25 -4120.75 -4147.25 -4173.75 -4200.25 -4226.75 -4253.25
Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5
H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
# 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621
Pad SEG354 SEG355 SEG356 SEG357 SEG358 SEG359 SEG360 SEG361 SEG362 SEG363 SEG364 SEG365 SEG366 SEG367 SEG368 SEG369 SEG370 SEG371 SEG372 SEG373 SEG374 SEG375 SEG376 SEG377 SEG378 SEG379 SEG380 SEG381 SEG382 SEG383 SEG384 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18
X -4279.75 -4306.25 -4332.75 -4359.25 -4385.75 -4412.25 -4438.75 -4465.25 -4491.75 -4518.25 -4544.75 -4571.25 -4597.75 -4624.25 -4650.75 -4677.25 -4703.75 -4730.25 -4756.75 -4783.25 -4809.75 -4836.25 -4862.75 -4889.25 -4915.75 -4942.25 -4968.75 -4995.25 -5021.75 -5048.25 -5074.75 -5101.25 -5127.75 -5154.25 -5180.75 -5207.25 -5233.75 -5260.25 -5286.75 -5313.25
Y 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533 533
W 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5 14.5
H 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138 138
Revision A_0.6
71
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999 ~ 2007
TRAY INFORMATION
H20-58x453-22
ULTRACHIP
INC.
72
ES Specifications
UC1697V
128x128RGB CSTN Controller-Driver
REVISION HISTORY
Revision 0.6 Contents First Release Date of Rev. Feb. 7, 2007
Revision A_0.6
73

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